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[209.132.180.67]) by mx.google.com with ESMTP id q76-v6si754539pfa.91.2018.10.12.02.23.29; Fri, 12 Oct 2018 02:23:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728191AbeJLQy1 (ORCPT + 99 others); Fri, 12 Oct 2018 12:54:27 -0400 Received: from mail-qt1-f196.google.com ([209.85.160.196]:37404 "EHLO mail-qt1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727885AbeJLQy1 (ORCPT ); Fri, 12 Oct 2018 12:54:27 -0400 Received: by mail-qt1-f196.google.com with SMTP id d14-v6so13141434qto.4 for ; Fri, 12 Oct 2018 02:22:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=BDzXhZnxU4cCMt0EkvgGsmZGFAvXzzlQY5OtoRL7IOA=; b=C8PIlgF4lzKIVUNbQYHVFovFC1mGBNlJBBXHUUmc8KW6hNMh9Z4zQ4KS+meQeBe+rl 4IlIvBG1eq550JAvoAzBU4r91QupFr2ve5Y5IFXzaQOk9qMag317fY7I+XQniZWi3wF7 htNw+cvvSyC9QS685rVW3s0S6zugMXqutLCIoeUJ85dTRIpUjYSl3thcauFhvGnAK4Nn BPqYYp26MI4fdxptXlBk1uWQL5CeYDDIaU/JOBEKcIpfa0NynW5gmOaRdrmXlOIy5Ggi oRICnbdUapG5MWlaPayllb2OedL1x+fYItrVjUCBPTKMd5RzrbmCN2Cl570sHijh3rUy Ofyw== X-Gm-Message-State: ABuFfogdp64TpLja2q3JbfremHrf9WyQRBDUdbCHnMzzqmg9TQS25vLa zVec8Zw1KKUsydSZHiRgHdgDoi+I/3X+wvhIm3M= X-Received: by 2002:ac8:2bf0:: with SMTP id n45-v6mr5008260qtn.152.1539336176852; Fri, 12 Oct 2018 02:22:56 -0700 (PDT) MIME-Version: 1.0 References: <1539224450-19928-1-git-send-email-vincentc@andestech.com> <1539224450-19928-2-git-send-email-vincentc@andestech.com> <20181012084945.GB10286@andestech.com> In-Reply-To: <20181012084945.GB10286@andestech.com> From: Arnd Bergmann Date: Fri, 12 Oct 2018 11:22:40 +0200 Message-ID: Subject: Re: [PATCH v2 1/5] nds32: nds32 FPU port To: Vincent Chen Cc: Vincent Chen , Linux Kernel Mailing List , Greentime Hu Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 12, 2018 at 10:52 AM Vincent Chen wrote: > > On Thu, Oct 11, 2018 at 03:30:30PM +0800, Arnd Bergmann wrote: > > On Thu, Oct 11, 2018 at 4:56 AM Vincent Chen wrote: > > There was a long discussion on RISC-V about what happens when > > FPU support is enabled or disabled, you may have seen that as well. > > > > Can you confirm that: > > > > a) A kernel with FPU support enabled running on a CPU without an FPU > > will behave the same as a kernel without FPU support, and in particular > > not crash while trying to access the FPU > > b) A kernel with FPU support disabled running on a CPU with an FPU > > prevents user space from accessing the FPU, to avoid corrupting > > FPU registers during a task switch when a process accidentally contains > > FPU access > > In this patch user program will be terminated when accessing FPU register > if the FPU support is disabled on kernel. Hence, condition b) is promised. > Condition a) is unsupported in this patch. I will add this support in > the next version patch. Ok, sounds good, thanks Arnd