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References: <20181011185458.10186-1-kristen@linux.intel.com> <CALCETrW5sNz-TO8w8e+7d1oD_CmnUX_txnBuKe2+wM7qFaK64A@mail.gmail.com>
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From:   Samuel Neves <sneves@dei.uc.pt>
Date:   Fri, 12 Oct 2018 10:20:25 +0100
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Subject: Re: [PATCH] x86: entry: flush the cache if syscall error
To:     Andy Lutomirski <luto@kernel.org>
Cc:     kristen@linux.intel.com,
        Kernel Hardening <kernel-hardening@lists.openwall.com>,
        Thomas Gleixner <tglx@linutronix.de>,
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On Thu, Oct 11, 2018 at 8:25 PM Andy Lutomirski <luto@kernel.org> wrote:
> What exactly is this trying to protect against?  And how many cycles
> should we expect L1D_FLUSH to take?

As far as I could measure, I got 1660 cycles per wrmsr 0x10b, 0x1 on a
Skylake chip, and 1220 cycles on a Skylake-SP.