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[209.132.180.67]) by mx.google.com with ESMTP id l6-v6si1303378pgh.373.2018.10.12.08.04.19; Fri, 12 Oct 2018 08:04:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728996AbeJLWgi convert rfc822-to-8bit (ORCPT + 99 others); Fri, 12 Oct 2018 18:36:38 -0400 Received: from www.llwyncelyn.cymru ([82.70.14.225]:49928 "EHLO fuzix.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728646AbeJLWgh (ORCPT ); Fri, 12 Oct 2018 18:36:37 -0400 Received: from alans-desktop (82-70-14-226.dsl.in-addr.zen.co.uk [82.70.14.226]) by fuzix.org (8.15.2/8.15.2) with ESMTP id w9CF2KE6027233; Fri, 12 Oct 2018 16:02:20 +0100 Date: Fri, 12 Oct 2018 16:02:19 +0100 From: Alan Cox To: Andy Lutomirski Cc: Andy Lutomirski , Kees Cook , Kristen Carlson Accardi , Kernel Hardening , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , X86 ML , LKML Subject: Re: [PATCH] x86: entry: flush the cache if syscall error Message-ID: <20181012160219.7d16ef59@alans-desktop> In-Reply-To: <77F59E25-5244-4CBC-A3CB-DCF863803CD2@amacapital.net> References: <20181011185458.10186-1-kristen@linux.intel.com> <20181012152515.1d816906@alans-desktop> <77F59E25-5244-4CBC-A3CB-DCF863803CD2@amacapital.net> Organization: Intel Corporation X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > My understanding is that the standard “breadcrumb” is that a cache line is fetched into L1D, and that the cacheline in question will go into L1D even if it was previously not cached at all. So flushing L1D will cause the timing from a probe to be different, but the breadcrumb is still there, and the attack will still work. Flush not write back. The L1D is empty (or full of other stuff the way the prototype I tested did it as x86 lacked a true L1 flushing primitive) > > At best you have a microscopic window to attack it on the SMT pair. > > So only the extra clever attackers will pull it off. This isn’t all that reassuring. It's going to be very hard for them to do that. You don't really have the timing control in userspace to do that sort of thing easily. At the end of the day it's an additional hardenening not a fix. It's designed to provide extra protection for the cases we don't know about until we find them and lfence them. All of this (and all sidechannel of any kind) is merely about reducing the bandwidth an attacker can achieve. The idea is that it's cheap enough that it's worth doing. > Or I would get a fancy new CPU and use UMONITOR and, unless UMONITOR is much cleverer than I suspect it is, the gig is up. The time window for the attack could be as small as you want, and UMONITOR will catch it. That would be an interesting line of attack. You would still have to navigate a fair bit of noise. Alan