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From:   Benjamin Gaignard <benjamin.gaignard@linaro.org>
Date:   Mon, 15 Oct 2018 13:15:30 +0200
Message-ID: <CA+M3ks4GR5tw_YDTjWNO7mwUx5BhuBsc=5_dzNNMCYnGO08X+Q@mail.gmail.com>
Subject: Re: [PATCH v1 2/2] drm/stm: ltdc: Solve issue on pixel clock & data
 enable polarity
To:     Yannick Fertre <yannick.fertre@st.com>
Cc:     Philippe Cornu <philippe.cornu@st.com>,
        Benjamin GAIGNARD <benjamin.gaignard@st.com>,
        Vincent Abriou <vincent.abriou@st.com>,
        Gustavo Padovan <gustavo@padovan.org>,
        Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
        sean@poorly.run, David Airlie <airlied@linux.ie>,
        ML dri-devel <dri-devel@lists.freedesktop.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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Sender: linux-kernel-owner@vger.kernel.org
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Le lun. 24 sept. 2018 =C3=A0 14:05, Yannick Fertr=C3=A9 <yannick.fertre@st.=
com> a =C3=A9crit :
>
> Wrong flags used for set the pixel clock & data enable polarities.
> Add trace for polarities of hsync, vsync, data enabled & pixel clock.
>
> Signed-off-by: Yannick Fertr=C3=A9 <yannick.fertre@st.com>
Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
> ---
>  drivers/gpu/drm/stm/ltdc.c | 23 +++++++++++++++++++----
>  1 file changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index 808d9fb..f671abc 100644
> --- a/drivers/gpu/drm/stm/ltdc.c
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -517,7 +517,7 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *=
crtc)
>         struct videomode vm;
>         u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
>         u32 total_width, total_height;
> -       u32 val;
> +       u32 val =3D 0;
>
>         drm_display_mode_to_videomode(mode, &vm);
>
> @@ -538,7 +538,22 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc =
*crtc)
>         total_height =3D accum_act_h + vm.vfront_porch;
>
>         /* Configures the HS, VS, DE and PC polarities. Default Active Lo=
w */
> -       val =3D 0;
> +       if (vm.flags & DISPLAY_FLAGS_HSYNC_LOW)
> +               DRM_DEBUG_DRIVER("Horizontal Synchronization polarity is =
active low");
> +       if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
> +               DRM_DEBUG_DRIVER("Horizontal Synchronization polarity is =
active high");
> +       if (vm.flags & DISPLAY_FLAGS_VSYNC_LOW)
> +               DRM_DEBUG_DRIVER("Vertical Synchronization polarity is ac=
tive low");
> +       if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
> +               DRM_DEBUG_DRIVER("Vertical Synchronization polarity is ac=
tive high");
> +       if (vm.flags & DISPLAY_FLAGS_DE_LOW)
> +               DRM_DEBUG_DRIVER("Data Enable polarity is active low");
> +       if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
> +               DRM_DEBUG_DRIVER("Data Enable polarity is active high");
> +       if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
> +               DRM_DEBUG_DRIVER("Pixel clock polarity is active low");
> +       if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
> +               DRM_DEBUG_DRIVER("Pixel clock polarity is active high");
>
>         if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
>                 val |=3D GCR_HSPOL;
> @@ -546,10 +561,10 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc=
 *crtc)
>         if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
>                 val |=3D GCR_VSPOL;
>
> -       if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
> +       if (vm.flags & DISPLAY_FLAGS_DE_LOW)
>                 val |=3D GCR_DEPOL;
>
> -       if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
> +       if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
>                 val |=3D GCR_PCPOL;
>
>         reg_update_bits(ldev->regs, LTDC_GCR,
> --
> 2.7.4
>
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