Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Date:   Mon, 15 Oct 2018 14:26:52 +0100
From:   Mark Rutland <mark.rutland@arm.com>
To:     Marek Szyprowski <m.szyprowski@samsung.com>
Cc:     linux-samsung-soc@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        Will Deacon <will.deacon@arm.com>,
        Catalin Marinas <catalin.marinas@arm.com>,
        Marc Zyngier <marc.zyngier@arm.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Krzysztof Kozlowski <krzk@kernel.org>,
        Chanwoo Choi <cw00.choi@samsung.com>,
        Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>,
        Inki Dae <inki.dae@samsung.com>, nd@arm.com
Subject: Re: [PATCH v2 3/6] clocksource: exynos_mct: Add arch_timer
 cooperation mode for ARM64
Message-ID: <20181015132652.3vanslay7xomtzqh@lakrids.cambridge.arm.com>
References: <20181015123112.9379-1-m.szyprowski@samsung.com>
 <CGME20181015123135eucas1p16a10ed68040141a714ab2977e2ad5e2d@eucas1p1.samsung.com>
 <20181015123112.9379-4-m.szyprowski@samsung.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20181015123112.9379-4-m.szyprowski@samsung.com>
User-Agent: NeoMutt/20170113 (1.7.2)
NoDisclaimer: True
Received-SPF: None (protection.outlook.com: arm.com does not designate
 permitted sender hosts)
SpamDiagnosticOutput: 1:99
SpamDiagnosticMetadata: NSPM
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2018 13:26:55.0444
 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: 780385f7-4e0e-4920-661c-08d632a1e04f
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR08MB2988
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Mon, Oct 15, 2018 at 02:31:09PM +0200, Marek Szyprowski wrote:
> To get ARM Architected Timers working on Samsung Exynos SoCs, one has to
> first configure and enable Exynos Multi-Core Timer, because they both
> share some common hardware blocks.

Could you please elaborate on what exactly is shared with the MCT?

Architecturally, the OS shouldn't have to do anything to put the timers
into a usable state. All instances should be fed (directly) from the
system counter, which FW is tasked with configuring and enabling, and
all other state is private to the instance.

If we have to poke things to make them usable, that means we can't
assume that it's always safe to use the timers or counters, as the
architecture lets us, and I'd like to understand what the impact is.

e.g. does this mean that there are windows where the counters don't
tick?

Are all the counters fed the same underlying counter value? ... or are
those independent?

Thanks,
Mark.

> This patch adds a mode of cooperation with arch_timer driver, so
> kernel can use CP15 based timer interface via arch_timer driver, which
> is mandatory on ARM64. In such mode driver only configures MCT
> registers and starts the timer but don't register any clocksource or
> events in the system. Those are left to be handled by arch_timer
> driver.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/clocksource/exynos_mct.c | 52 +++++++++++++++++++++-----------
>  1 file changed, 35 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
> index a379f11fad2d..06cd30a6d59a 100644
> --- a/drivers/clocksource/exynos_mct.c
> +++ b/drivers/clocksource/exynos_mct.c
> @@ -57,6 +57,7 @@
>  #define TICK_BASE_CNT	1
>  
>  enum {
> +	MCT_INT_NONE = 0,
>  	MCT_INT_SPI,
>  	MCT_INT_PPI
>  };
> @@ -238,6 +239,9 @@ static int __init exynos4_clocksource_init(void)
>  {
>  	exynos4_mct_frc_start();
>  
> +	if (!mct_int_type)
> +		return 0;
> +
>  #if defined(CONFIG_ARM)
>  	exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
>  	exynos4_delay_timer.freq = clk_rate;
> @@ -343,6 +347,9 @@ static struct irqaction mct_comp_event_irq = {
>  
>  static int exynos4_clockevent_init(void)
>  {
> +	if (!mct_int_type)
> +		return 0;
> +
>  	mct_comp_device.cpumask = cpumask_of(0);
>  	clockevents_config_and_register(&mct_comp_device, clk_rate,
>  					0xf, 0xffffffff);
> @@ -476,12 +483,12 @@ static int exynos4_mct_starting_cpu(unsigned int cpu)
>  
>  		irq_force_affinity(evt->irq, cpumask_of(cpu));
>  		enable_irq(evt->irq);
> -	} else {
> +	} else if (mct_int_type == MCT_INT_PPI) {
>  		enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
>  	}
> -	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
> -					0xf, 0x7fffffff);
> -
> +	if (mct_int_type)
> +		clockevents_config_and_register(evt,
> +			       clk_rate / (TICK_BASE_CNT + 1), 0xf, 0x7fffffff);
>  	return 0;
>  }
>  
> @@ -496,7 +503,7 @@ static int exynos4_mct_dying_cpu(unsigned int cpu)
>  		if (evt->irq != -1)
>  			disable_irq_nosync(evt->irq);
>  		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
> -	} else {
> +	} else if (mct_int_type == MCT_INT_PPI) {
>  		disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
>  	}
>  	return 0;
> @@ -529,7 +536,7 @@ static int __init exynos4_timer_resources(struct device_node *np, void __iomem *
>  					 &percpu_mct_tick);
>  		WARN(err, "MCT: can't request IRQ %d (%d)\n",
>  		     mct_irqs[MCT_L0_IRQ], err);
> -	} else {
> +	} else if (mct_int_type == MCT_INT_SPI) {
>  		for_each_possible_cpu(cpu) {
>  			int mct_irq = mct_irqs[MCT_L0_IRQ + cpu];
>  			struct mct_clock_event_device *pcpu_mevt =
> @@ -564,7 +571,7 @@ static int __init exynos4_timer_resources(struct device_node *np, void __iomem *
>  out_irq:
>  	if (mct_int_type == MCT_INT_PPI) {
>  		free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
> -	} else {
> +	} else if (mct_int_type == MCT_INT_SPI) {
>  		for_each_possible_cpu(cpu) {
>  			struct mct_clock_event_device *pcpu_mevt =
>  				per_cpu_ptr(&percpu_mct_tick, cpu);
> @@ -585,17 +592,28 @@ static int __init mct_init_dt(struct device_node *np, unsigned int int_type)
>  
>  	mct_int_type = int_type;
>  
> -	/* This driver uses only one global timer interrupt */
> -	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
> +	if (IS_ENABLED(CONFIG_ARM64) && IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
> +		struct device_node *np = of_find_compatible_node(NULL, NULL,
> +							     "arm,armv8-timer");
> +		if (np) {
> +			mct_int_type = MCT_INT_NONE;
> +			of_node_put(np);
> +		}
> +	}
>  
> -	/*
> -	 * Find out the number of local irqs specified. The local
> -	 * timer irqs are specified after the four global timer
> -	 * irqs are specified.
> -	 */
> -	nr_irqs = of_irq_count(np);
> -	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
> -		mct_irqs[i] = irq_of_parse_and_map(np, i);
> +	if (mct_int_type) {
> +		/* This driver uses only one global timer interrupt */
> +		mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
> +
> +		/*
> +		 * Find out the number of local irqs specified. The local
> +		 * timer irqs are specified after the four global timer
> +		 * irqs are specified.
> +		 */
> +		nr_irqs = of_irq_count(np);
> +		for (i = MCT_L0_IRQ; i < nr_irqs; i++)
> +			mct_irqs[i] = irq_of_parse_and_map(np, i);
> +	}
>  
>  	ret = exynos4_timer_resources(np, of_iomap(np, 0));
>  	if (ret)
> -- 
> 2.17.1
>