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Miller" , Guan Xuetao , Max Filippov , arcml Subject: Re: [PATCH 12/18] arch/tlb: Clean up simple architectures Message-ID: <20181015141458.GQ9867@hirez.programming.kicks-ass.net> References: <20180926113623.863696043@infradead.org> <20180926114801.146189550@infradead.org> <20181011150406.GL9848@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 12, 2018 at 07:40:04PM +0000, Vineet Gupta wrote: > Very nice. Thx for doing this. > > Once you have redone this, please point me to a branch so I can give this a spin. > I've always been interested in tracking down / optimizing the full TLB flushes - > which ARC implements by simply moving the MMU/process to a new ASID (TLB entries > tagged with an 8 bit value - unique per process). When I started looking into this > , a simple ls (fork+execve) would increment the ASID by 13 which I'd optimized to > a reasonable 4. Haven't checked that in recent times though so would be fun to > revive that measurement. I just pushed out the latest version to: git://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git mm/tlb (mandatory caution: that tree is unstable / throw-away) I'll wait a few days to see what, if anything, comes back from 0day before posting again.