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[209.132.180.67]) by mx.google.com with ESMTP id b27-v6si13645857pgb.156.2018.10.16.01.43.57; Tue, 16 Oct 2018 01:45:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PQIEfptf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727282AbeJPQ0g (ORCPT + 99 others); Tue, 16 Oct 2018 12:26:36 -0400 Received: from mail-qk1-f194.google.com ([209.85.222.194]:44792 "EHLO mail-qk1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727263AbeJPQ0g (ORCPT ); Tue, 16 Oct 2018 12:26:36 -0400 Received: by mail-qk1-f194.google.com with SMTP id y8-v6so13569311qka.11 for ; Tue, 16 Oct 2018 01:37:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Ubyjo42R+HubJmEREUzTpsPrkU4zre0fUGpTagWB4sw=; b=PQIEfptf8M46zzD1bks1h1Pae9z2YUj3wesKEzX92MvbHjVJLAzBgRfC6/UF3RjE6Y PnL68nd47I5xNrAAYdhbaCqIojkfzZ6u6J4QOypxKegVzZXqAI3T8XnBIut3DZ+goXuk aARPKOpESn2XkGDjEBqttp+74wGRm/5WJ8DM0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Ubyjo42R+HubJmEREUzTpsPrkU4zre0fUGpTagWB4sw=; b=fgtVjYj9FzRYqJMGHLN5eITXWVvFuJjzxwbLMMVXR3bSXXGN4c7KmP+pha/Bx56Qh1 bncOPjU5w5KmuB5rJLzmFOc0CQdvTs8dQSLRfpmBeX1Y2C824+nMBq3pn5XlcXH7298K Au+t96/l4/BBgzuhGo8vVXGrit2EJyCrYZ9HFi0Gt1jIwkRJc/EPwxOt5GEsSM2ov0xo 7+ncS+vuu0Ay54VXC7kPbLCdC1CKdYBMK25gOW6EcQ6nqJ2b1JmGkgkucmvrlotQvLWd JkAUezdgpIN9GLkPqghBU/6Yfe61dG731RDSzkxJ30nSkRpl+bpmOM3NLH9zofgtHlyG HuNA== X-Gm-Message-State: ABuFfoiDTAk6umNKeHphVHkafy4ckZA9mTq7kyuWpOf1qA/qlUjHaWtM 31cxOeCqMRGdALf1Hm9iQLuLtD/XMKHUEzXu8M4kaA== X-Received: by 2002:a37:7282:: with SMTP id n124-v6mr20009923qkc.78.1539679028406; Tue, 16 Oct 2018 01:37:08 -0700 (PDT) MIME-Version: 1.0 References: <20181008191411.32555-1-manivannan.sadhasivam@linaro.org> In-Reply-To: <20181008191411.32555-1-manivannan.sadhasivam@linaro.org> From: Linus Walleij Date: Tue, 16 Oct 2018 10:36:56 +0200 Message-ID: Subject: Re: [PATCH 0/5] Add initial pinctrl support for MT6797 SoC To: Manivannan Sadhasivam , Sean Wang Cc: Matthias Brugger , Rob Herring , "open list:GPIO SUBSYSTEM" , "linux-kernel@vger.kernel.org" , Linux ARM , "moderated list:ARM/Mediatek SoC support" , Amit Kucheria Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 8, 2018 at 9:14 PM Manivannan Sadhasivam wrote: > This patchset adds initial pinctrl support for Mediatek MT6797 SoC. > The pinctrl driver is based on the vendor binding as like MT6765 and > implements only GPIO and pinmux functionalities. > > The devicetree binding doc is not added because it does not exist for > MT6765 and I'm not sure about the structure of it. > > This patchset has been tested on 96Boards MediatekX20 development board. I'd be delighted to merge the pin control bindings and driver as soon as I have an OK from Sean Wang. Yours, Linus Walleij