Received: by 2002:ac0:a582:0:0:0:0:0 with SMTP id m2-v6csp435201imm; Wed, 17 Oct 2018 02:38:01 -0700 (PDT) X-Google-Smtp-Source: ACcGV62+xkLtugL5HxjLnB/ez15yNMZAc99YPiBxZPb38ARQvrRPhTB+kj1aQqE0tUV0B/ySRZCr X-Received: by 2002:a63:904a:: with SMTP id a71-v6mr24347068pge.264.1539769081876; Wed, 17 Oct 2018 02:38:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539769081; cv=none; d=google.com; s=arc-20160816; b=lISiNFIjNd4WTR7aF5OskTwTJRMfXPVkOWc2XYe+WL8OcmwTAUFYqz3nr+suNkdDOG +dlim1ViGw1yUI1qVP45Xs9aKlHWHlR6OO3SBxCOfJ6P1VY1tKa6+/pQPkuw7qCgLETU EB8SqDMukOdyybOR6OrbeRugErHNHe1SmRnvYcr4x8/j7ZwBiFjCrEuhpYE7RROtKBt0 TqY5F3hGABdYGZLmZtWvLGK5ceqxPoZYaewBC0jTWrdGmcQ1lxdIRy+0tFVMXlLgTrb9 3YT0mhAWc0WDN5H6bawDt6lZcCixt6xf15n+XtAhwiCt4PHvszJxZKC9r6IRLq2LT+O9 Y1NQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from; bh=unj2iiDnbgROnadS3nABDBjHgGo3mDsn8R5OXCyw3uE=; b=hZtHlZ+/kyW+gxH9FklpBDJesFoT8gUElFXdjH6sJxjr+M/WlRXRYJkqoJhsq3U9l8 Uxb5YTDGXE441uRXwkRV8EtYZ7gJKbDnsfIllOKIyzpoSEEA4t5HdtuFPa7dDexXXBfd ECHNr7kgHV2VsATnWgbjojlpcoOZGgFPSLdm20Esdvpm3t3xmH2oSvxKv89volevp0rD fZ7gyibuhNCDnKkjTJZG217FweOUeol4Xb3W99YcFbmpXUmEacKdam0OxuhyPgsMMMkV eFXL6OVvw8aAcZda7ZiOoRs6TSxjGoj2AUo34wUmusUiZzVUphKBw+MN3feHVsRCh7oQ symw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a80-v6si17737714pfj.195.2018.10.17.02.37.45; Wed, 17 Oct 2018 02:38:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726974AbeJQRcL (ORCPT + 99 others); Wed, 17 Oct 2018 13:32:11 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:65527 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726691AbeJQRcL (ORCPT ); Wed, 17 Oct 2018 13:32:11 -0400 X-UUID: c175b17d1fa142cdb9a04879eb92a158-20181017 X-UUID: c175b17d1fa142cdb9a04879eb92a158-20181017 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 834201519; Wed, 17 Oct 2018 17:37:14 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 17 Oct 2018 17:37:12 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkcas08.mediatek.inc (172.21.101.126) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 17 Oct 2018 17:37:12 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 17 Oct 2018 17:37:12 +0800 From: To: Sean Wang , Vinod Koul , "Rob Herring" , Matthias Brugger , "Dan Williams" CC: , , , , , Subject: [PATCH v2] add support for Mediatek Command-Queue DMA controller on MT6765 SoC Date: Wed, 17 Oct 2018 17:36:57 +0800 Message-ID: <1539769019-32107-1-git-send-email-shun-chih.yu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Changes since v1: - remove unused macros, typos - leverage ASYNC_TX_ENABLE_CHANNEL_SWITCH to maintain DMA descriptor list This patchset introduces support for MediaTek Command-Queue DMA controller. MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated to memory-to-memory transfer through queue-based descriptor management. There are only 3 physical channels inside CQDMA, while the driver is extended to support 32 virtual channels for multiple dma users to issue dma requests onto the CQDMA simultaneously. Shun-Chih Yu (2): dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC .../devicetree/bindings/dma/mtk-cqdma.txt | 31 + drivers/dma/mediatek/Kconfig | 13 + drivers/dma/mediatek/Makefile | 1 + drivers/dma/mediatek/mtk-cqdma.c | 943 ++++++++++++++++++++ 4 files changed, 988 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt create mode 100644 drivers/dma/mediatek/mtk-cqdma.c