Received: by 2002:ac0:a582:0:0:0:0:0 with SMTP id m2-v6csp449876imm; Wed, 17 Oct 2018 02:56:34 -0700 (PDT) X-Google-Smtp-Source: ACcGV61b4Fo62X+T/3feUrTzkxfMgUwfrXk+J2qa6xCpBQ82wSo1x3Bj92ipkulIbSzosd5wzBPJ X-Received: by 2002:a17:902:b7c3:: with SMTP id v3-v6mr25569573plz.182.1539770194861; Wed, 17 Oct 2018 02:56:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539770194; cv=none; d=google.com; s=arc-20160816; b=REBCL2teqsR/j9Zgdna1G7FluSLNPlCvZwjKnnZ7dtIFVgvb5sd44L1gjFEtTVj69T jnEmpQq6i0G0fqE91DWHoZbcMc50LJVvPN+HfgHhv5jrTgUaBk6RVQ1PDv5FXNpyizVq 3tRXTnebQ2b3lOvSpblZU2B3mnTP05QR0kOhDYWB5jxiNE2izWWpgx2kdShNi8+leZyY hz6L93hjEllHm7Z2ES4Ayc/RlUF7S9PAIJ4IcmIpHlsgjGbKZFQSaJsyLLw9eDedaVlU bs7QkleDzaM0McvhV93EEeOz3NqWCwDekMFkdxXSzZ8ww0nmSBH+Yi1p71ghX1HVx5OP 7MdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:references:cc:to:from:subject; bh=Ek5uwfjJJydXTstdQNhl42aY1ck+tR/v4kY9CGRCioU=; b=LUUn8bBFnkLtRo4wH8JtkLoYY0AYIRcRMbhJlfjGvu1YgNHYaipuomkzuSFAa3jrSo RbgaDgW8SR43b8ajKHUvjuBwMRd0BeAHU5300I46qnJsv9KUVl2OHlM79Ss48Z4tIK8i 9iYCy3iU9+d4EeKz0u3TG9m039DkCtOZt4RIFAj9oPSUCClaZgWi54V+tenKjAjbvoTk hiq3nE4LVJpQemj5pG8bN36NOH+QApddgsOKy5Ww05y+Br/bUxINE5hKGvL4Og9dEyOm 0CUFUZZJgyx5wbvhJQRU9bgp4q+Is0fu2YtI8ET4eUpL0J9KLn6IUxLUdv/jHzTvl5CL Hifg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b="jI2OU/q2"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l9-v6si17119995pfi.179.2018.10.17.02.56.19; Wed, 17 Oct 2018 02:56:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b="jI2OU/q2"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727054AbeJQRtc (ORCPT + 99 others); Wed, 17 Oct 2018 13:49:32 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17262 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726936AbeJQRtc (ORCPT ); Wed, 17 Oct 2018 13:49:32 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 17 Oct 2018 02:54:33 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 17 Oct 2018 02:54:37 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 17 Oct 2018 02:54:37 -0700 Received: from [10.26.11.110] (172.20.13.39) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 17 Oct 2018 09:54:33 +0000 Subject: Re: [PATCH v1 3/5] ARM: tegra: Create tegra20-cpufreq device on Tegra30 From: Jon Hunter To: Dmitry Osipenko , Thierry Reding , Peter De Schrijver , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring CC: , , , References: <20180830194356.14059-1-digetx@gmail.com> <20180830194356.14059-4-digetx@gmail.com> <9ec51c2d-02f6-0988-0940-0ec31d22f697@nvidia.com> Message-ID: <65532de7-2768-0d99-33a9-5b43cfbf510c@nvidia.com> Date: Wed, 17 Oct 2018 10:54:30 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <9ec51c2d-02f6-0988-0940-0ec31d22f697@nvidia.com> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL106.nvidia.com (172.18.146.12) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1539770073; bh=Ek5uwfjJJydXTstdQNhl42aY1ck+tR/v4kY9CGRCioU=; h=X-PGP-Universal:Subject:From:To:CC:References:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=jI2OU/q2j2hrCVU1u/OQIGYcFAhgHojQu4t7pKGNZeG8+ILMusIsySd/B2im1SS1b Qp8wZkZIeIzTh8m9rVWnUojtBjqdRvGLF3Bccuay2fMXPRU9KxL2cgtyfer9M1YczI Saq/AehsOuZ4goJP7Mi19X88CXNvDJQxaYNv9zdr0KM0vRzbvwPGvON/eAFyuVKvJO /7QbKs+8Iqnrc6DY11VK5eIqqAXdItAMfGMB3Zur/YHwvAr3XKTnQvgvDQKg0+ZmLC xXsSvchuqAOVO7zJJduvciuUZAtIPm5lnHn4xO+OE0Y7UAKyD92jpzEupZxX7XYmtQ YrzVKdF+7rRVg== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/10/2018 09:49, Jon Hunter wrote: > > On 30/08/2018 20:43, Dmitry Osipenko wrote: >> Tegra20-cpufreq driver require a platform device in order to be loaded, >> instantiate a simple platform device for the driver during of the machines >> late initialization. Driver now supports Tegra30 SoC's, hence create the >> device on Tegra30 machines. >> >> Signed-off-by: Dmitry Osipenko >> --- >> arch/arm/mach-tegra/tegra.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c >> index 67d8ae60ac67..b559e22eab76 100644 >> --- a/arch/arm/mach-tegra/tegra.c >> +++ b/arch/arm/mach-tegra/tegra.c >> @@ -111,6 +111,10 @@ static void __init tegra_dt_init_late(void) >> if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && >> of_machine_is_compatible("nvidia,tegra20")) >> platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); >> + >> + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && >> + of_machine_is_compatible("nvidia,tegra30")) >> + platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); >> } >> >> static const char * const tegra_dt_board_compat[] = { > > Not sure why you would do this if now the driver only works with DT. Am > I missing something? Actually, not sure why we just don't move this into the actual driver itself like we have for tegra124. Cheers Jon -- nvpublic