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From: Jon Hunter Message-ID: <3c72f573-d109-b607-b7b7-d70aea3e03df@nvidia.com> Date: Wed, 17 Oct 2018 14:34:05 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1539783244; bh=EugO07srDsUXCHppSJ5HLETkrHxBjlxbVnIMa5dyd3M=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=XVEiKyrNZyOzqfFciRyCFldKHelXQbIPkCxJxU09EHmZbm39OJjVw4s6tQo9frkls XZY3PestpRoFpT4HSr6ieuMPheghW4AntIwAGdOSOHzixJILZG2R/ML/XCeaNagyZZ n87IWPvwlaGa7xP5M9ORjkYBxeofa0vPAOrY6O9L8MsXDbc5ODSc9GBtNEryauRQS+ en9J8vGJxWGGqj3FgPVFJR7H4MlO2IP9Hibd/Vcs3+0cc8qMRd5Uaq0AuXlw/P3glg 8iv+IcQ2vyLHXBCU+HT68EHNVdJJHdzeHPmC6+yghm3resKbg4Uc4P199oAFv1a+9y pEH3VbNv7QJMg== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/10/2018 14:07, Dmitry Osipenko wrote: > On 10/17/18 3:59 PM, Jon Hunter wrote: >> >> On 17/10/2018 13:37, Dmitry Osipenko wrote: >>> On 10/17/18 11:40 AM, Jon Hunter wrote: >>>> >>>> On 30/08/2018 20:43, Dmitry Osipenko wrote: >>>>> Add device-tree binding that describes CPU frequency-scaling hardware >>>>> found on NVIDIA Tegra20/30 SoC's. >>>>> >>>>> Signed-off-by: Dmitry Osipenko >>>>> --- >>>>> .../cpufreq/nvidia,tegra20-cpufreq.txt | 38 +++++++++++++++++++ >>>>> 1 file changed, 38 insertions(+) >>>>> create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt >>>>> new file mode 100644 >>>>> index 000000000000..2c51f676e958 >>>>> --- /dev/null >>>>> +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt >>>>> @@ -0,0 +1,38 @@ >>>>> +Binding for NVIDIA Tegra20 CPUFreq >>>>> +================================== >>>>> + >>>>> +Required properties: >>>>> +- clocks: Must contain an entry for each entry in clock-names. >>>>> + See ../clocks/clock-bindings.txt for details. >>>>> +- clock-names: Must include the following entries: >>>>> + - pll_x: main-parent for CPU clock, must be the first entry >>>>> + - backup: intermediate-parent for CPU clock >>>>> + - cpu: the CPU clock >>>> >>>> Is it likely that 'backup' will be anything other that pll_p? If not why >>>> not just call it pll_p? Personally, I don't 'backup' to descriptive even >>>> though I can see what you mean. >>>> >>>> I can see that you want to make this flexible, but if the likelihood is >>>> that we will just use pll_p then I am not sure it is warranted at this >>>> point. >>> >>> That won't describe HW, but software. And device tree should describe HW. >> >> Hmm ... well that's my point exactly. So why call it 'backup'? Sounds >> like a software description to me. > > Because HW is designed the way that CPU parent need to be switched to the backup clock source while main clock changes its rate. HW also allow to select among different parents, pll_p is one of those parents. Yes that part is understood. I am just splitting hairs over the actual name. We do the same for tegra124 but we just call it 'pll_p'. See ... Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt Cheers Jon -- nvpublic