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[209.132.180.67]) by mx.google.com with ESMTP id v6-v6si21730991plg.84.2018.10.17.22.08.03; Wed, 17 Oct 2018 22:08:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727396AbeJRNGs (ORCPT + 99 others); Thu, 18 Oct 2018 09:06:48 -0400 Received: from mail-sh2.amlogic.com ([58.32.228.45]:28728 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727328AbeJRNGs (ORCPT ); Thu, 18 Oct 2018 09:06:48 -0400 Received: from localhost.localdomain (10.18.11.217) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Thu, 18 Oct 2018 13:07:27 +0800 From: Jianxin Pan To: Jerome Brunet , Neil Armstrong CC: Jianxin Pan , Kevin Hilman , Carlo Caione , Michael Turquette , Stephen Boyd , Rob Herring , Miquel Raynal , Boris Brezillon , Martin Blumenstingl , Yixun Lan , Liang Yang , Jian Hu , Qiufang Dai , Hanjie Lin , Victor Wan , , , , , Subject: [PATCH v5 0/3] clk: meson: add a sub EMMC clock controller support Date: Thu, 18 Oct 2018 13:07:22 +0800 Message-ID: <1539839245-13793-1-git-send-email-jianxin.pan@amlogic.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.18.11.217] Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This driver will add a MMC clock controller driver support. The original idea about adding a clock controller is during the discussion in the NAND driver mainline effort[1]. This driver is tested in the S400 board (AXG platform) with NAND driver. Changes since v4 [5]: - use struct parm in phase delay driver - remove 0 delay releted part in phase delay driver - don't rebuild the parent name once again - add divider ops with .init Changes since v3 [4]: - separate clk-phase-delay driver - replace clk_get_rate() with clk_hw_get_rate() - collect Rob's R-Y - drop 'meson-' prefix from compatible string Changes since v2 [3]: - squash dt-binding clock-id patch - update license - fix alignment - construct a clk register helper() function Changes since v1 [2]: - implement phase clock - update compatible name - adjust file name - divider probe() into small functions, and re-use them [1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13 [2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun.lan@amlogic.com [3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun.lan@amlogic.com [4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun.lan@amlogic.com [5] https://lkml.kernel.org/r/20180809070724.11935-4-yixun.lan@amlogic.com Yixun Lan (3): clk: meson: add emmc sub clock phase delay driver clk: meson: add DT documentation for emmc clock controller clk: meson: add sub MMC clock controller driver .../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 31 +++ drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile | 3 +- drivers/clk/meson/clk-phase-delay.c | 79 ++++++ drivers/clk/meson/clk-regmap.c | 27 +- drivers/clk/meson/clk-regmap.h | 1 + drivers/clk/meson/clkc.h | 13 + drivers/clk/meson/mmc-clkc.c | 296 +++++++++++++++++++++ include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++ 9 files changed, 475 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt create mode 100644 drivers/clk/meson/clk-phase-delay.c create mode 100644 drivers/clk/meson/mmc-clkc.c create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h -- 1.9.1