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From:   Vivek Gautam <vivek.gautam@codeaurora.org>
Date:   Thu, 18 Oct 2018 17:03:06 +0530
Message-ID: <CAFp+6iHRECKosJWQZoaZa6QxAmW0MZLNPsFAbD21vW+kG0xJ-A@mail.gmail.com>
Subject: Re: [PATCH 1/2] arm64: dts: qcom: sdm845: add UFS controller
To:     evgreen@chromium.org
Cc:     Andy Gross <andy.gross@linaro.org>,
        David Brown <david.brown@linaro.org>,
        "robh+dt" <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        linux-arm-msm <linux-arm-msm@vger.kernel.org>,
        "open list:ARM/QUALCOMM SUPPORT" <linux-soc@vger.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        open list <linux-kernel@vger.kernel.org>, swboyd@chromium.org,
        Doug Anderson <dianders@chromium.org>
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Hi Evan,

On Wed, Oct 17, 2018 at 10:55 PM Evan Green <evgreen@chromium.org> wrote:
>
> This change adds the UFS controller and PHY to SDM845.
>
> Signed-off-by: Evan Green <evgreen@chromium.org>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> ---
>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 66 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 66 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index b72bdb0a31a5..20b2c258816a 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -808,6 +808,72 @@
>                         };
>                 };
>
> +               ufshc1: ufshc@1d84000 {
> +                       compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
> +                                    "jedec,ufs-2.0";
> +                       reg = <0x1d84000 0x2500>;
> +                       interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> +                       phys = <&ufsphy1_lanes>;
> +                       phy-names = "ufsphy";
> +                       lanes-per-direction = <2>;
> +                       power-domains = <&gcc UFS_PHY_GDSC>;
> +
> +                       clock-names =
> +                               "core_clk",
> +                               "bus_aggr_clk",
> +                               "iface_clk",
> +                               "core_clk_unipro",
> +                               "ref_clk",
> +                               "tx_lane0_sync_clk",
> +                               "rx_lane0_sync_clk",
> +                               "rx_lane1_sync_clk";
> +                       clocks =
> +                               <&gcc GCC_UFS_PHY_AXI_CLK>,
> +                               <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> +                               <&gcc GCC_UFS_PHY_AHB_CLK>,
> +                               <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> +                               <&rpmhcc RPMH_CXO_CLK>,
> +                               <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> +                               <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> +                               <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> +                       freq-table-hz =
> +                               <50000000 200000000>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <37500000 150000000>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <0 0>;
> +
> +                       resets = <&gcc GCC_UFS_PHY_BCR>;
> +                       reset-names = "rst";
> +
> +                       status = "disabled";
> +               };
> +
> +               ufsphy1: ufsphy@1d87000 {

nit: s/ufsphy@1d87000/phy@1d87000

> +                       compatible = "qcom,sdm845-qmp-ufs-phy";
> +                       reg = <0x1d87000 0x18c>;
> +                       #clock-cells = <1>;

why do we need this clock-cells? ufsphy i think is not providing any
clocks. Is it?
Rest looks good.

Best regards
Vivek

> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +                       clock-names = "ref",
> +                                     "ref_aux";
> +                       clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
> +                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> +
> +                       status = "disabled";
> +
> +                       ufsphy1_lanes: lanes@1d87400 {
> +                               reg = <0x1d87400 0x108>,
> +                                     <0x1d87600 0x1e0>,
> +                                     <0x1d87c00 0x1dc>;
> +                               #phy-cells = <0>;
> +                       };
> +               };
> +
>                 tcsr_mutex_regs: syscon@1f40000 {
>                         compatible = "syscon";
>                         reg = <0x1f40000 0x40000>;
> --
> 2.16.4
>


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