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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: b1503c74-a6c8-4c58-7a27-08d635af1169 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Oct 2018 10:38:54.6396 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB2313 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Radhey Shyam Pandey > Sent: Saturday, September 29, 2018 10:48 PM > To: vkoul@kernel.org; dan.j.williams@intel.com; Michal Simek > ; Appana Durga Kedareswara Rao > ; Radhey Shyam Pandey > Cc: dmaengine@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linu= x- > kernel@vger.kernel.org > Subject: [PATCH v2 4/4] dmaengine: xilinx_dma: Fix 64-bit simple CDMA > transfer >=20 > In AXI CDMA simple mode also pass MSB bits of source and destination > address to xilinx_write function. This fixes simple CDMA operation mode u= sing > 64-bit addressing. >=20 > Signed-off-by: Radhey Shyam Pandey > Signed-off-by: Michal Simek Reviewed-by: Appana Durga Kedareswara Rao Regards, Kedar. > --- > Changes for v2: > Use helper macro for preparing dma_addr_t. > --- > drivers/dma/xilinx/xilinx_dma.c | 6 ++++-- > 1 files changed, 4 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_= dma.c > index c27ab64..d04ef85 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -1247,8 +1247,10 @@ static void xilinx_cdma_start_transfer(struct > xilinx_dma_chan *chan) >=20 > hw =3D &segment->hw; >=20 > - xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw- > >src_addr); > - xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw- > >dest_addr); > + xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, > + xilinx_prep_dma_addr_t(hw->src_addr)); > + xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, > + xilinx_prep_dma_addr_t(hw->dest_addr)); >=20 > /* Start the transfer */ > dma_ctrl_write(chan, XILINX_DMA_REG_BTT, > -- > 1.7.1