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[209.132.180.67]) by mx.google.com with ESMTP id d5-v6si12498403pla.372.2018.10.19.08.51.06; Fri, 19 Oct 2018 08:51:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727706AbeJSX5O (ORCPT + 99 others); Fri, 19 Oct 2018 19:57:14 -0400 Received: from mail-sh2.amlogic.com ([58.32.228.45]:47289 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726935AbeJSX5O (ORCPT ); Fri, 19 Oct 2018 19:57:14 -0400 Received: from [192.168.0.111] (223.166.104.93) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server (TLS) id 15.0.1320.4; Fri, 19 Oct 2018 23:50:14 +0800 Subject: Re: [PATCH v5 2/3] clk: meson: add DT documentation for emmc clock controller To: Stephen Boyd , Jerome Brunet , Neil Armstrong CC: Yixun Lan , Kevin Hilman , Carlo Caione , Michael Turquette , Rob Herring , Miquel Raynal , Boris Brezillon , Martin Blumenstingl , Liang Yang , Jian Hu , Qiufang Dai , Hanjie Lin , Victor Wan , , , , References: <1539839245-13793-1-git-send-email-jianxin.pan@amlogic.com> <1539839245-13793-3-git-send-email-jianxin.pan@amlogic.com> <153988248599.5275.8444799485095155762@swboyd.mtv.corp.google.com> From: Jianxin Pan Message-ID: Date: Fri, 19 Oct 2018 23:50:08 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <153988248599.5275.8444799485095155762@swboyd.mtv.corp.google.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [223.166.104.93] X-ClientProxiedBy: mail-sh2.amlogic.com (10.18.11.6) To mail-sh2.amlogic.com (10.18.11.6) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2018/10/19 1:08, Stephen Boyd wrote: > Quoting Jianxin Pan (2018-10-17 22:07:24) >> diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt >> new file mode 100644 >> index 0000000..9e6d343 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt >> @@ -0,0 +1,31 @@ >> +* Amlogic MMC Sub Clock Controller Driver >> + >> +The Amlogic MMC clock controller generates and supplies clock to support >> +MMC and NAND controller >> + >> +Required Properties: >> + >> +- compatible: should be: >> + "amlogic,gx-mmc-clkc" >> + "amlogic,axg-mmc-clkc" >> + >> +- #clock-cells: should be 1. >> +- clocks: phandles to clocks corresponding to the clock-names property >> +- clock-names: list of parent clock names >> + - "clkin0", "clkin1" >> + >> +Parent node should have the following properties : > > The example only has one node. Can you add two nodes? OK. This clock is used by nand and emmc. I will add a new example for emmc too. Thank you for your review. > >> +- compatible: "amlogic,axg-mmc-clkc", "syscon". >> +- reg: base address and size of the MMC control register space. >> + >> +Example: Clock controller node: >> + >> +sd_mmc_c_clkc: clock-controller@7000 { >> + compatible = "amlogic,axg-mmc-clkc", "syscon"; >> + reg = <0x0 0x7000 0x0 0x4>; >> + #clock-cells = <1>; >> + >> + clock-names = "clkin0", "clkin1"; >> + clocks = <&clkc CLKID_SD_MMC_C_CLK0>, >> + <&clkc CLKID_FCLK_DIV2>; >> +}; > > . >