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[209.132.180.67]) by mx.google.com with ESMTP id bd3-v6si7253362plb.399.2018.10.25.05.58.37; Thu, 25 Oct 2018 05:58:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=iBN1xabN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727427AbeJYVar (ORCPT + 99 others); Thu, 25 Oct 2018 17:30:47 -0400 Received: from mail.kernel.org ([198.145.29.99]:43358 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727240AbeJYVar (ORCPT ); Thu, 25 Oct 2018 17:30:47 -0400 Received: from mail-qk1-f182.google.com (mail-qk1-f182.google.com [209.85.222.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 201A820840; Thu, 25 Oct 2018 12:58:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1540472287; bh=3FkoqUQ+gY6SrsUHv+8in/oTANUFQUq26YcpK03ambE=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=iBN1xabNvhluiPtMrhZg9NL4B7rfc9pkn1CBREurbCZ7Tj/HNRJuvrflltAbiqJxr oW74oXVNgx7/G8aS3rb+kRHI2NoiuHEm7G6bej7Rb4FVoPA8YNGKuiLy8QalqdP8Z1 ZfrlHqUspHlfmTxYBPydU/UrtRqan8l0pDqby3/k= Received: by mail-qk1-f182.google.com with SMTP id m8-v6so5577044qka.12; Thu, 25 Oct 2018 05:58:07 -0700 (PDT) X-Gm-Message-State: AGRZ1gLgk8nAGNTOnnyECPFqS+eNDX3pNbSZ24flDsmGBWxkCZbDDSkp SP//oAS3vYOMTgLVw3SdHhBToy/81OisIdOf/w== X-Received: by 2002:ae9:ef14:: with SMTP id d20mr1134613qkg.147.1540472286228; Thu, 25 Oct 2018 05:58:06 -0700 (PDT) MIME-Version: 1.0 References: <1539853324-29051-1-git-send-email-p.paillet@st.com> <1539853324-29051-2-git-send-email-p.paillet@st.com> <20181025094430.GQ4939@dell> In-Reply-To: <20181025094430.GQ4939@dell> From: Rob Herring Date: Thu, 25 Oct 2018 07:57:53 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 1/8] dt-bindings: mfd: document stpmic1 To: Lee Jones Cc: Pascal PAILLET-LME , Dmitry Torokhov , Mark Rutland , Liam Girdwood , Mark Brown , Wim Van Sebroeck , Guenter Roeck , linux-input@vger.kernel.org, devicetree@vger.kernel.org, "linux-kernel@vger.kernel.org" , LINUX-WATCHDOG , Benjamin Gaignard , Enric Balletbo i Serra Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 25, 2018 at 4:44 AM Lee Jones wrote: > > Rob: please grep your name for some feedback. > > On Thu, 18 Oct 2018, Pascal PAILLET-LME wrote: > > > From: pascal paillet > > +Optional parent device properties: > > +- st,main-control-register: > > + -bit 1: Power cycling will be performed on turn OFF condition > > + -bit 2: PWRCTRL is functional > > + -bit 3: PWRCTRL active high > > +- st,pads-pull-register: > > + -bit 1: WAKEUP pull down is not active > > + -bit 2: PWRCTRL pull up is active > > + -bit 3: PWRCTRL pull down is active > > + -bit 4: WAKEUP detector is disabled > > +- st,vin-control-register: > > + -bit 0: VINLOW monitoring is enabled > > + -bit [1...3]: VINLOW rising threshold > > + 000 VINOK_f + 50mV > > + 001 VINOK_f + 100mV > > + 010 VINOK_f + 150mV > > + 011 VINOK_f + 200mV > > + 100 VINOK_f + 250mV > > + 101 VINOK_f + 300mV > > + 110 VINOK_f + 350mV > > + 111 VINOK_f + 400mV > > + -bit [4...5]: VINLOW hyst > > + 00 100mV > > + 01 200mV > > + 10 300mV > > + 11 400mV > > + -bit 6: SW_OUT detector is disabled > > + -bit 7: SW_IN detector is enabled. > > +- st,usb-control-register: > > + -bit 3: SW_OUT current limit > > + 0: 600mA > > + 1: 1.1A > > + -bit 4: VBUS_OTG discharge is enabled > > + -bit 5: SW_OUT discharge is enabled > > + -bit 6: VBUS_OTG detection is enabled > > + -bit 7: BOOST_OVP is disabled > > I'm surprised Rob allowed you to add register bits in a DT property? Yeah, they are certainly questionable and not something we encourage, but the alternative would be dozens of properties which only apply for this one device and just get translated back to register values. Rob