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[209.85.167.169]) by smtp.gmail.com with ESMTPSA id m40sm3590588otd.68.2018.10.25.12.49.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Oct 2018 12:49:28 -0700 (PDT) Received: by mail-oi1-f169.google.com with SMTP id k64-v6so7737502oia.13; Thu, 25 Oct 2018 12:49:28 -0700 (PDT) X-Received: by 2002:aca:220c:: with SMTP id b12-v6mr349719oic.203.1540496967974; Thu, 25 Oct 2018 12:49:27 -0700 (PDT) MIME-Version: 1.0 References: <1540407376-24115-1-git-send-email-vabhav.sharma@nxp.com> <1540407376-24115-6-git-send-email-vabhav.sharma@nxp.com> In-Reply-To: <1540407376-24115-6-git-send-email-vabhav.sharma@nxp.com> From: Li Yang Date: Thu, 25 Oct 2018 14:49:16 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v6 5/6] arm64: dts: add QorIQ LX2160A SoC support To: Vabhav Sharma Cc: Sudeep Holla , Scott Wood , lkml , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Rob Herring , Mark Rutland , linuxppc-dev , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Michael Turquette , sboyd@kernel.org, "Rafael J. Wysocki" , Viresh Kumar , linux-clk , linux-pm@vger.kernel.org, linux-kernel-owner@vger.kernel.org, Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Arnd Bergmann , Kate Stewart , yamada.masahiro@socionext.com, Shawn Guo , Russell King , Adrian Hunter , Ulf Hansson , V.Sethi@nxp.com, udit.kumar@nxp.com, pankaj.bansal@nxp.com, Ramneek Mehresh , Ying Zhang , nipun.gupta@nxp.com, Priyanka Jain , yogeshnarayan.gaur@nxp.com, Sriram Dash , Horia Geanta , Ran Wang , Yinbo Zhu Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 25, 2018 at 2:03 AM Vabhav Sharma wrote: > > LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture. > > LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores > in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C > controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA > UARTs etc. > > Signed-off-by: Ramneek Mehresh > Signed-off-by: Zhang Ying-22455 > Signed-off-by: Nipun Gupta > Signed-off-by: Priyanka Jain > Signed-off-by: Yogesh Gaur > Signed-off-by: Sriram Dash > Signed-off-by: Vabhav Sharma > Signed-off-by: Horia Geanta > Signed-off-by: Ran Wang > Signed-off-by: Yinbo Zhu > --- > arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 766 +++++++++++++++++++++++++ > 1 file changed, 766 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > new file mode 100644 > index 0000000..9fcfd48 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > @@ -0,0 +1,766 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +// > +// Device Tree Include file for Layerscape-LX2160A family SoC. > +// > +// Copyright 2018 NXP > + > +#include > +#include > + > +/memreserve/ 0x80000000 0x00010000; > + > +/ { > + compatible = "fsl,lx2160a"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + // 8 clusters having 2 Cortex-A72 cores each > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x0>; > + clocks = <&clockgen 1 0>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster0_l2>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x1>; > + clocks = <&clockgen 1 0>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster0_l2>; > + }; > + > + cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x100>; > + clocks = <&clockgen 1 1>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster1_l2>; > + }; > + > + cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x101>; > + clocks = <&clockgen 1 1>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster1_l2>; > + }; > + > + cpu@200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x200>; > + clocks = <&clockgen 1 2>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster2_l2>; > + }; > + > + cpu@201 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x201>; > + clocks = <&clockgen 1 2>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster2_l2>; > + }; > + > + cpu@300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x300>; > + clocks = <&clockgen 1 3>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster3_l2>; > + }; > + > + cpu@301 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x301>; > + clocks = <&clockgen 1 3>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster3_l2>; > + }; > + > + cpu@400 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x400>; > + clocks = <&clockgen 1 4>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster4_l2>; > + }; > + > + cpu@401 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x401>; > + clocks = <&clockgen 1 4>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster4_l2>; > + }; > + > + cpu@500 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x500>; > + clocks = <&clockgen 1 5>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster5_l2>; > + }; > + > + cpu@501 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x501>; > + clocks = <&clockgen 1 5>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster5_l2>; > + }; > + > + cpu@600 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x600>; > + clocks = <&clockgen 1 6>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster6_l2>; > + }; > + > + cpu@601 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x601>; > + clocks = <&clockgen 1 6>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster6_l2>; > + }; > + > + cpu@700 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x700>; > + clocks = <&clockgen 1 7>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster7_l2>; > + }; > + > + cpu@701 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; > + reg = <0x701>; > + clocks = <&clockgen 1 7>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster7_l2>; > + }; > + > + cluster0_l2: l2-cache0 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + > + cluster1_l2: l2-cache1 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + > + cluster2_l2: l2-cache2 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + > + cluster3_l2: l2-cache3 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + > + cluster4_l2: l2-cache4 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + > + cluster5_l2: l2-cache5 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + > + cluster6_l2: l2-cache6 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + > + cluster7_l2: l2-cache7 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + }; > + > + gic: interrupt-controller@6000000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x06000000 0 0x10000>, // GIC Dist > + <0x0 0x06200000 0 0x200000>, // GICR (RD_base + > + // SGI_base) > + <0x0 0x0c0c0000 0 0x2000>, // GICC > + <0x0 0x0c0d0000 0 0x1000>, // GICH > + <0x0 0x0c0e0000 0 0x20000>; // GICV > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + interrupts = ; > + > + its: gic-its@6020000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + reg = <0x0 0x6020000 0 0x20000>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + }; > + > + pmu { > + compatible = "arm,cortex-a72-pmu"; > + interrupts = ; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + memory@80000000 { > + // DRAM space - 1, size : 2 GB DRAM > + device_type = "memory"; > + reg = <0x00000000 0x80000000 0 0x80000000>; > + }; > + > + ddr1: memory-controller@1080000 { > + compatible = "fsl,qoriq-memory-controller"; > + reg = <0x0 0x1080000 0x0 0x1000>; > + interrupts = ; > + little-endian; > + }; > + > + ddr2: memory-controller@1090000 { > + compatible = "fsl,qoriq-memory-controller"; > + reg = <0x0 0x1090000 0x0 0x1000>; > + interrupts = ; > + little-endian; > + }; > + > + // One clock unit-sysclk node which bootloader require during DT fix-up > + sysclk: sysclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; Would be even better if you can add a comment "fixed up by bootloader" to the property too. > + clock-output-names = "sysclk"; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + crypto: crypto@8000000 { > + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; > + fsl,sec-era = <10>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x00 0x8000000 0x100000>; > + reg = <0x00 0x8000000 0x0 0x100000>; > + interrupts = ; > + dma-coherent; > + status = "disabled"; > + > + sec_jr0: jr@10000 { > + compatible = "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x10000 0x10000>; > + interrupts = ; > + }; > + > + sec_jr1: jr@20000 { > + compatible = "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x20000 0x10000>; > + interrupts = ; > + }; > + > + sec_jr2: jr@30000 { > + compatible = "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x30000 0x10000>; > + interrupts = ; > + }; > + > + sec_jr3: jr@40000 { > + compatible = "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x40000 0x10000>; > + interrupts = ; > + }; > + }; > + > + clockgen: clock-controller@1300000 { > + compatible = "fsl,lx2160a-clockgen"; > + reg = <0 0x1300000 0 0xa0000>; > + #clock-cells = <2>; > + clocks = <&sysclk>; > + }; > + > + dcfg: syscon@1e00000 { > + compatible = "fsl,lx2160a-dcfg", "syscon"; > + reg = <0x0 0x1e00000 0x0 0x10000>; > + little-endian; > + }; > + > + i2c0: i2c@2000000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2000000 0x0 0x10000>; > + interrupts = ; > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; > + status = "disabled"; > + }; > + > + i2c1: i2c@2010000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2010000 0x0 0x10000>; > + interrupts = ; > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + status = "disabled"; > + }; > + > + i2c2: i2c@2020000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2020000 0x0 0x10000>; > + interrupts = ; > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + status = "disabled"; > + }; > + > + i2c3: i2c@2030000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2030000 0x0 0x10000>; > + interrupts = ; > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + status = "disabled"; > + }; > + > + i2c4: i2c@2040000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2040000 0x0 0x10000>; > + interrupts = ; > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; > + status = "disabled"; > + }; > + > + i2c5: i2c@2050000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2050000 0x0 0x10000>; > + interrupts = ; > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + status = "disabled"; > + }; > + > + i2c6: i2c@2060000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2060000 0x0 0x10000>; > + interrupts = ; > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + status = "disabled"; > + }; > + > + i2c7: i2c@2070000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2070000 0x0 0x10000>; > + interrupts = ; > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + status = "disabled"; > + }; > + > + esdhc0: esdhc@2140000 { > + compatible = "fsl,esdhc"; > + reg = <0x0 0x2140000 0x0 0x10000>; > + interrupts = <0 28 0x4>; /* Level high type */ > + clocks = <&clockgen 4 1>; > + voltage-ranges = <1800 1800 3300 3300>; > + sdhci,auto-cmd12; > + little-endian; > + bus-width = <4>; > + status = "disabled"; > + }; > + > + esdhc1: esdhc@2150000 { > + compatible = "fsl,esdhc"; > + reg = <0x0 0x2150000 0x0 0x10000>; > + interrupts = <0 63 0x4>; /* Level high type */ > + clocks = <&clockgen 4 1>; > + voltage-ranges = <1800 1800 3300 3300>; > + sdhci,auto-cmd12; > + broken-cd; > + little-endian; > + bus-width = <4>; > + status = "disabled"; > + }; > + > + uart0: serial@21c0000 { > + compatible = "arm,sbsa-uart","arm,pl011"; > + reg = <0x0 0x21c0000 0x0 0x1000>; > + interrupts = ; > + current-speed = <115200>; > + status = "disabled"; > + }; > + > + uart1: serial@21d0000 { > + compatible = "arm,sbsa-uart","arm,pl011"; > + reg = <0x0 0x21d0000 0x0 0x1000>; > + interrupts = ; > + current-speed = <115200>; > + status = "disabled"; > + }; > + > + uart2: serial@21e0000 { > + compatible = "arm,sbsa-uart","arm,pl011"; > + reg = <0x0 0x21e0000 0x0 0x1000>; > + interrupts = ; > + current-speed = <115200>; > + status = "disabled"; > + }; > + > + uart3: serial@21f0000 { > + compatible = "arm,sbsa-uart","arm,pl011"; > + reg = <0x0 0x21f0000 0x0 0x1000>; > + interrupts = ; > + current-speed = <115200>; > + status = "disabled"; > + }; > + > + gpio0: gpio@2300000 { > + compatible = "fsl,qoriq-gpio"; > + reg = <0x0 0x2300000 0x0 0x10000>; > + interrupts = ; > + gpio-controller; > + little-endian; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio1: gpio@2310000 { > + compatible = "fsl,qoriq-gpio"; > + reg = <0x0 0x2310000 0x0 0x10000>; > + interrupts = ; > + gpio-controller; > + little-endian; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio2: gpio@2320000 { > + compatible = "fsl,qoriq-gpio"; > + reg = <0x0 0x2320000 0x0 0x10000>; > + interrupts = ; > + gpio-controller; > + little-endian; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio3: gpio@2330000 { > + compatible = "fsl,qoriq-gpio"; > + reg = <0x0 0x2330000 0x0 0x10000>; > + interrupts = ; > + gpio-controller; > + little-endian; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + watchdog@23a0000 { > + compatible = "arm,sbsa-gwdt"; > + reg = <0x0 0x23a0000 0 0x1000>, > + <0x0 0x2390000 0 0x1000>; > + interrupts = ; > + timeout-sec = <30>; > + }; > + > + usb0: usb@3100000 { > + compatible = "snps,dwc3"; > + reg = <0x0 0x3100000 0x0 0x10000>; > + interrupts = ; > + dr_mode = "host"; > + snps,quirk-frame-length-adjustment = <0x20>; > + snps,dis_rxdet_inp3_quirk; > + status = "disabled"; > + }; > + > + usb1: usb@3110000 { > + compatible = "snps,dwc3"; > + reg = <0x0 0x3110000 0x0 0x10000>; > + interrupts = ; > + dr_mode = "host"; > + snps,quirk-frame-length-adjustment = <0x20>; > + snps,dis_rxdet_inp3_quirk; > + status = "disabled"; > + }; > + > + smmu: iommu@5000000 { > + compatible = "arm,mmu-500"; > + reg = <0 0x5000000 0 0x800000>; > + #iommu-cells = <1>; > + #global-interrupts = <14>; > + // global secure fault > + interrupts = , > + // combined secure > + , > + // global non-secure fault > + , > + // combined non-secure > + , > + // performance counter interrupts 0-9 > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + // per context interrupt, 64 interrupts > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + dma-coherent; > + }; > + }; > +}; > -- > 2.7.4 >