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(dtynxhybvjnm1yvtdwgvt-3.rev.dnainternet.fi. [2001:14ba:8017:3300:313a:d550:4603:9163]) by smtp.googlemail.com with ESMTPSA id h26-v6sm512870lfc.40.2018.10.25.13.53.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Oct 2018 13:53:58 -0700 (PDT) Subject: Re: [PATCH v2 3/3] reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller. To: Nava kishore Manne , p.zabel@pengutronix.de, robh+dt@kernel.org, mark.rutland@arm.com, michal.simek@xilinx.com, rajanv@xilinx.com, jollys@xilinx.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, chinnikishore369@gmail.com References: <20181026122424.30831-1-nava.manne@xilinx.com> <20181026122424.30831-4-nava.manne@xilinx.com> From: =?UTF-8?B?VmVzYSBKw6TDpHNrZWzDpGluZW4=?= Message-ID: <437c1bc9-8d5b-7b2a-f612-993151c23f7c@gmail.com> Date: Thu, 25 Oct 2018 23:53:56 +0300 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20181026122424.30831-4-nava.manne@xilinx.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Some comments below. On 26/10/2018 15.24, Nava kishore Manne wrote: > Add a reset controller driver for Xilinx Zynq UltraScale+ MPSoC. > The zynqmp reset-controller has the ability to reset lines > connected to different blocks and peripheral in the Soc. > > Signed-off-by: Nava kishore Manne > --- > Changes for v2: > -Fixed some minor coding issues as suggested > by philipp. > > Changes for v1: > -None. > > Changes for RFC-V3: > -None. > > Changes for RFC-V2: > -Moved eemi_ops into a priv struct as suggested > by philipp. > > drivers/reset/Makefile | 1 + > drivers/reset/reset-zynqmp.c | 114 +++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 115 insertions(+) > create mode 100644 drivers/reset/reset-zynqmp.c > > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index 4243c38..eb315d1 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -24,4 +24,5 @@ obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o > obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o > obj-$(CONFIG_RESET_UNIPHIER_USB3) += reset-uniphier-usb3.o > obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o > +obj-$(CONFIG_ARCH_ZYNQMP) += reset-zynqmp.o > > diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c > new file mode 100644 > index 0000000..cff63d9 > --- /dev/null > +++ b/drivers/reset/reset-zynqmp.c > @@ -0,0 +1,114 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2018 Xilinx, Inc. > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START - 2) Probably should be: +#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START - 1) or if START is moved one forward: +#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START) > +#define ZYNQMP_RESET_ID (ZYNQMP_PM_RESET_START + 1) If you move start forward then you don't need +1 here. Or you can get rid of the define altogether and just use ZYNQMP_PM_RESET_START in it's place.. Thanks, Vesa Jääskeläinen