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[209.132.180.67]) by mx.google.com with ESMTP id q9-v6si14211990pfk.27.2018.10.26.23.25.46; Fri, 26 Oct 2018 23:26:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728197AbeJ0PDC (ORCPT + 99 others); Sat, 27 Oct 2018 11:03:02 -0400 Received: from mail3-relais-sop.national.inria.fr ([192.134.164.104]:40762 "EHLO mail3-relais-sop.national.inria.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726610AbeJ0PDC (ORCPT ); Sat, 27 Oct 2018 11:03:02 -0400 X-IronPort-AV: E=Sophos;i="5.54,430,1534802400"; d="scan'208";a="283492153" Received: from palace.rsr.lip6.fr (HELO palace.lip6.fr) ([132.227.105.202]) by mail3-relais-sop.national.inria.fr with ESMTP/TLS/AES128-SHA256; 27 Oct 2018 08:22:58 +0200 From: Julia Lawall To: Michael Turquette Cc: kernel-janitors@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/8] clk: pistachio: constify clk_ops structures Date: Sat, 27 Oct 2018 07:47:38 +0200 Message-Id: <1540619262-22681-5-git-send-email-Julia.Lawall@lip6.fr> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1540619262-22681-1-git-send-email-Julia.Lawall@lip6.fr> References: <1540619262-22681-1-git-send-email-Julia.Lawall@lip6.fr> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These clk_ops structures are only stored in the ops field of a clk_init_data structure. This field is const, so the clk_ops structures can be const as well. Identified and transformed using Coccinelle. Signed-off-by: Julia Lawall --- drivers/clk/pistachio/clk-pll.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/pistachio/clk-pll.c b/drivers/clk/pistachio/clk-pll.c index 7e8daab9025b..312c3580187f 100644 --- a/drivers/clk/pistachio/clk-pll.c +++ b/drivers/clk/pistachio/clk-pll.c @@ -298,7 +298,7 @@ static unsigned long pll_gf40lp_frac_recalc_rate(struct clk_hw *hw, return rate; } -static struct clk_ops pll_gf40lp_frac_ops = { +static const struct clk_ops pll_gf40lp_frac_ops = { .enable = pll_gf40lp_frac_enable, .disable = pll_gf40lp_frac_disable, .is_enabled = pll_gf40lp_frac_is_enabled, @@ -307,7 +307,7 @@ static struct clk_ops pll_gf40lp_frac_ops = { .set_rate = pll_gf40lp_frac_set_rate, }; -static struct clk_ops pll_gf40lp_frac_fixed_ops = { +static const struct clk_ops pll_gf40lp_frac_fixed_ops = { .enable = pll_gf40lp_frac_enable, .disable = pll_gf40lp_frac_disable, .is_enabled = pll_gf40lp_frac_is_enabled, @@ -430,7 +430,7 @@ static unsigned long pll_gf40lp_laint_recalc_rate(struct clk_hw *hw, return rate; } -static struct clk_ops pll_gf40lp_laint_ops = { +static const struct clk_ops pll_gf40lp_laint_ops = { .enable = pll_gf40lp_laint_enable, .disable = pll_gf40lp_laint_disable, .is_enabled = pll_gf40lp_laint_is_enabled, @@ -439,7 +439,7 @@ static struct clk_ops pll_gf40lp_laint_ops = { .set_rate = pll_gf40lp_laint_set_rate, }; -static struct clk_ops pll_gf40lp_laint_fixed_ops = { +static const struct clk_ops pll_gf40lp_laint_fixed_ops = { .enable = pll_gf40lp_laint_enable, .disable = pll_gf40lp_laint_disable, .is_enabled = pll_gf40lp_laint_is_enabled,