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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 2aIoUsYa8QLzgJaaMQT0MfARfKEv0+oWPhZllonTzOz/12SbHX2mAdoLTk26c/99akh534eZhbVR31MSUsaAZd1v1oMVoWm14FUIFvF8tmMVg5CYCcROjf/SqogCgSX7RMpdtZEyZSaOp9B0PJ346pwWNyBLVpwZFQ2IhepRMslo96sN9HzU3+cyMaKcX9mljXs1VH/Gm6i1APTw4I0PatuEF5AZfMk0mNnyehpP+ofgfNWaz9nr96LoClohBd/l6rrVVWWFRf/jYvm1nx8KvnBNr37RiGagVm/6yDGmNbijdZnk6dqLbcWpQ/Zb4KbgYJK5dUn0kyFT06H62blUfqGrk7ETf6hhLCCCceT+rpE= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1353ab77-a5bb-4fb4-a8ba-08d63d7c9d4b X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Oct 2018 08:57:54.8567 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5149 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture. LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA UARTs etc. Signed-off-by: Ramneek Mehresh Signed-off-by: Zhang Ying-22455 Signed-off-by: Nipun Gupta Signed-off-by: Priyanka Jain Signed-off-by: Yogesh Gaur Signed-off-by: Sriram Dash Signed-off-by: Vabhav Sharma Signed-off-by: Horia Geanta Signed-off-by: Ran Wang Signed-off-by: Yinbo Zhu --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 766 +++++++++++++++++++++= ++++ 1 file changed, 766 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-lx2160a.dtsi new file mode 100644 index 0000000..a79f5c1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -0,0 +1,766 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree Include file for Layerscape-LX2160A family SoC. +// +// Copyright 2018 NXP + +#include +#include + +/memreserve/ 0x80000000 0x00010000; + +/ { + compatible =3D "fsl,lx2160a"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + // 8 clusters having 2 Cortex-A72 cores each + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x0>; + clocks =3D <&clockgen 1 0>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster0_l2>; + }; + + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x1>; + clocks =3D <&clockgen 1 0>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster0_l2>; + }; + + cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x100>; + clocks =3D <&clockgen 1 1>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster1_l2>; + }; + + cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x101>; + clocks =3D <&clockgen 1 1>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster1_l2>; + }; + + cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x200>; + clocks =3D <&clockgen 1 2>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster2_l2>; + }; + + cpu@201 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x201>; + clocks =3D <&clockgen 1 2>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster2_l2>; + }; + + cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x300>; + clocks =3D <&clockgen 1 3>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster3_l2>; + }; + + cpu@301 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x301>; + clocks =3D <&clockgen 1 3>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster3_l2>; + }; + + cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x400>; + clocks =3D <&clockgen 1 4>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster4_l2>; + }; + + cpu@401 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x401>; + clocks =3D <&clockgen 1 4>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster4_l2>; + }; + + cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x500>; + clocks =3D <&clockgen 1 5>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster5_l2>; + }; + + cpu@501 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x501>; + clocks =3D <&clockgen 1 5>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster5_l2>; + }; + + cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x600>; + clocks =3D <&clockgen 1 6>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster6_l2>; + }; + + cpu@601 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x601>; + clocks =3D <&clockgen 1 6>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster6_l2>; + }; + + cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x700>; + clocks =3D <&clockgen 1 7>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster7_l2>; + }; + + cpu@701 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + enable-method =3D "psci"; + reg =3D <0x701>; + clocks =3D <&clockgen 1 7>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0xC000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <192>; + next-level-cache =3D <&cluster7_l2>; + }; + + cluster0_l2: l2-cache0 { + compatible =3D "cache"; + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-level =3D <2>; + }; + + cluster1_l2: l2-cache1 { + compatible =3D "cache"; + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-level =3D <2>; + }; + + cluster2_l2: l2-cache2 { + compatible =3D "cache"; + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-level =3D <2>; + }; + + cluster3_l2: l2-cache3 { + compatible =3D "cache"; + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-level =3D <2>; + }; + + cluster4_l2: l2-cache4 { + compatible =3D "cache"; + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-level =3D <2>; + }; + + cluster5_l2: l2-cache5 { + compatible =3D "cache"; + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-level =3D <2>; + }; + + cluster6_l2: l2-cache6 { + compatible =3D "cache"; + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-level =3D <2>; + }; + + cluster7_l2: l2-cache7 { + compatible =3D "cache"; + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-level =3D <2>; + }; + }; + + gic: interrupt-controller@6000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x06000000 0 0x10000>, // GIC Dist + <0x0 0x06200000 0 0x200000>, // GICR (RD_base + + // SGI_base) + <0x0 0x0c0c0000 0 0x2000>, // GICC + <0x0 0x0c0d0000 0 0x1000>, // GICH + <0x0 0x0c0e0000 0 0x20000>; // GICV + #interrupt-cells =3D <3>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + interrupt-controller; + interrupts =3D ; + + its: gic-its@6020000 { + compatible =3D "arm,gic-v3-its"; + msi-controller; + reg =3D <0x0 0x6020000 0 0x20000>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + pmu { + compatible =3D "arm,cortex-a72-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + memory@80000000 { + // DRAM space - 1, size : 2 GB DRAM + device_type =3D "memory"; + reg =3D <0x00000000 0x80000000 0 0x80000000>; + }; + + ddr1: memory-controller@1080000 { + compatible =3D "fsl,qoriq-memory-controller"; + reg =3D <0x0 0x1080000 0x0 0x1000>; + interrupts =3D ; + little-endian; + }; + + ddr2: memory-controller@1090000 { + compatible =3D "fsl,qoriq-memory-controller"; + reg =3D <0x0 0x1090000 0x0 0x1000>; + interrupts =3D ; + little-endian; + }; + + // One clock unit-sysclk node which bootloader require during DT fix-up + sysclk: sysclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100000000>; // fixed up by bootloader + clock-output-names =3D "sysclk"; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + crypto: crypto@8000000 { + compatible =3D "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era =3D <10>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x00 0x8000000 0x100000>; + reg =3D <0x00 0x8000000 0x0 0x100000>; + interrupts =3D ; + dma-coherent; + status =3D "disabled"; + + sec_jr0: jr@10000 { + compatible =3D "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg =3D <0x10000 0x10000>; + interrupts =3D ; + }; + + sec_jr1: jr@20000 { + compatible =3D "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg =3D <0x20000 0x10000>; + interrupts =3D ; + }; + + sec_jr2: jr@30000 { + compatible =3D "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg =3D <0x30000 0x10000>; + interrupts =3D ; + }; + + sec_jr3: jr@40000 { + compatible =3D "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg =3D <0x40000 0x10000>; + interrupts =3D ; + }; + }; + + clockgen: clock-controller@1300000 { + compatible =3D "fsl,lx2160a-clockgen"; + reg =3D <0 0x1300000 0 0xa0000>; + #clock-cells =3D <2>; + clocks =3D <&sysclk>; + }; + + dcfg: syscon@1e00000 { + compatible =3D "fsl,lx2160a-dcfg", "syscon"; + reg =3D <0x0 0x1e00000 0x0 0x10000>; + little-endian; + }; + + i2c0: i2c@2000000 { + compatible =3D "fsl,vf610-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x2000000 0x0 0x10000>; + interrupts =3D ; + clock-names =3D "i2c"; + clocks =3D <&clockgen 4 7>; + scl-gpio =3D <&gpio2 15 GPIO_ACTIVE_HIGH>; + status =3D "disabled"; + }; + + i2c1: i2c@2010000 { + compatible =3D "fsl,vf610-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x2010000 0x0 0x10000>; + interrupts =3D ; + clock-names =3D "i2c"; + clocks =3D <&clockgen 4 7>; + status =3D "disabled"; + }; + + i2c2: i2c@2020000 { + compatible =3D "fsl,vf610-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x2020000 0x0 0x10000>; + interrupts =3D ; + clock-names =3D "i2c"; + clocks =3D <&clockgen 4 7>; + status =3D "disabled"; + }; + + i2c3: i2c@2030000 { + compatible =3D "fsl,vf610-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x2030000 0x0 0x10000>; + interrupts =3D ; + clock-names =3D "i2c"; + clocks =3D <&clockgen 4 7>; + status =3D "disabled"; + }; + + i2c4: i2c@2040000 { + compatible =3D "fsl,vf610-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x2040000 0x0 0x10000>; + interrupts =3D ; + clock-names =3D "i2c"; + clocks =3D <&clockgen 4 7>; + scl-gpio =3D <&gpio2 16 GPIO_ACTIVE_HIGH>; + status =3D "disabled"; + }; + + i2c5: i2c@2050000 { + compatible =3D "fsl,vf610-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x2050000 0x0 0x10000>; + interrupts =3D ; + clock-names =3D "i2c"; + clocks =3D <&clockgen 4 7>; + status =3D "disabled"; + }; + + i2c6: i2c@2060000 { + compatible =3D "fsl,vf610-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x2060000 0x0 0x10000>; + interrupts =3D ; + clock-names =3D "i2c"; + clocks =3D <&clockgen 4 7>; + status =3D "disabled"; + }; + + i2c7: i2c@2070000 { + compatible =3D "fsl,vf610-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x2070000 0x0 0x10000>; + interrupts =3D ; + clock-names =3D "i2c"; + clocks =3D <&clockgen 4 7>; + status =3D "disabled"; + }; + + esdhc0: esdhc@2140000 { + compatible =3D "fsl,esdhc"; + reg =3D <0x0 0x2140000 0x0 0x10000>; + interrupts =3D <0 28 0x4>; /* Level high type */ + clocks =3D <&clockgen 4 1>; + voltage-ranges =3D <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; + bus-width =3D <4>; + status =3D "disabled"; + }; + + esdhc1: esdhc@2150000 { + compatible =3D "fsl,esdhc"; + reg =3D <0x0 0x2150000 0x0 0x10000>; + interrupts =3D <0 63 0x4>; /* Level high type */ + clocks =3D <&clockgen 4 1>; + voltage-ranges =3D <1800 1800 3300 3300>; + sdhci,auto-cmd12; + broken-cd; + little-endian; + bus-width =3D <4>; + status =3D "disabled"; + }; + + uart0: serial@21c0000 { + compatible =3D "arm,sbsa-uart","arm,pl011"; + reg =3D <0x0 0x21c0000 0x0 0x1000>; + interrupts =3D ; + current-speed =3D <115200>; + status =3D "disabled"; + }; + + uart1: serial@21d0000 { + compatible =3D "arm,sbsa-uart","arm,pl011"; + reg =3D <0x0 0x21d0000 0x0 0x1000>; + interrupts =3D ; + current-speed =3D <115200>; + status =3D "disabled"; + }; + + uart2: serial@21e0000 { + compatible =3D "arm,sbsa-uart","arm,pl011"; + reg =3D <0x0 0x21e0000 0x0 0x1000>; + interrupts =3D ; + current-speed =3D <115200>; + status =3D "disabled"; + }; + + uart3: serial@21f0000 { + compatible =3D "arm,sbsa-uart","arm,pl011"; + reg =3D <0x0 0x21f0000 0x0 0x1000>; + interrupts =3D ; + current-speed =3D <115200>; + status =3D "disabled"; + }; + + gpio0: gpio@2300000 { + compatible =3D "fsl,qoriq-gpio"; + reg =3D <0x0 0x2300000 0x0 0x10000>; + interrupts =3D ; + gpio-controller; + little-endian; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpio1: gpio@2310000 { + compatible =3D "fsl,qoriq-gpio"; + reg =3D <0x0 0x2310000 0x0 0x10000>; + interrupts =3D ; + gpio-controller; + little-endian; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpio2: gpio@2320000 { + compatible =3D "fsl,qoriq-gpio"; + reg =3D <0x0 0x2320000 0x0 0x10000>; + interrupts =3D ; + gpio-controller; + little-endian; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpio3: gpio@2330000 { + compatible =3D "fsl,qoriq-gpio"; + reg =3D <0x0 0x2330000 0x0 0x10000>; + interrupts =3D ; + gpio-controller; + little-endian; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + watchdog@23a0000 { + compatible =3D "arm,sbsa-gwdt"; + reg =3D <0x0 0x23a0000 0 0x1000>, + <0x0 0x2390000 0 0x1000>; + interrupts =3D ; + timeout-sec =3D <30>; + }; + + usb0: usb@3100000 { + compatible =3D "snps,dwc3"; + reg =3D <0x0 0x3100000 0x0 0x10000>; + interrupts =3D ; + dr_mode =3D "host"; + snps,quirk-frame-length-adjustment =3D <0x20>; + snps,dis_rxdet_inp3_quirk; + status =3D "disabled"; + }; + + usb1: usb@3110000 { + compatible =3D "snps,dwc3"; + reg =3D <0x0 0x3110000 0x0 0x10000>; + interrupts =3D ; + dr_mode =3D "host"; + snps,quirk-frame-length-adjustment =3D <0x20>; + snps,dis_rxdet_inp3_quirk; + status =3D "disabled"; + }; + + smmu: iommu@5000000 { + compatible =3D "arm,mmu-500"; + reg =3D <0 0x5000000 0 0x800000>; + #iommu-cells =3D <1>; + #global-interrupts =3D <14>; + // global secure fault + interrupts =3D , + // combined secure + , + // global non-secure fault + , + // combined non-secure + , + // performance counter interrupts 0-9 + , + , + , + , + , + , + , + , + , + , + // per context interrupt, 64 interrupts + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-coherent; + }; + }; +}; --=20 2.7.4