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[209.132.180.67]) by mx.google.com with ESMTP id g67-v6si12548242plb.163.2018.10.30.05.08.59; Tue, 30 Oct 2018 05:09:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MuzQVs7T; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727952AbeJ3VBk (ORCPT + 99 others); Tue, 30 Oct 2018 17:01:40 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:34341 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727834AbeJ3VBk (ORCPT ); Tue, 30 Oct 2018 17:01:40 -0400 Received: by mail-lf1-f67.google.com with SMTP id n26-v6so8669045lfl.1 for ; Tue, 30 Oct 2018 05:08:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ikcapejhZs1NZVz+nd6VxP3ivNvG3HHZ13oWDtGHyD0=; b=MuzQVs7TLQXYLnlv5NK83Rwiud/j6ktYcTpRljzkYwYuFtd789l8uwxlsutoAq8Blo lKoaRr4x8QlnYuZsd24rc7OQcR/VrueBxGsUOcc5nrF1zqG6VdshbGg8E67kKDz/OlCn uvgyMzO8jAXTJb/IBXpVjTOjcVbSgqFj8jyOo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ikcapejhZs1NZVz+nd6VxP3ivNvG3HHZ13oWDtGHyD0=; b=bcDRjvIfIDPFPCaJoRHxhkiH9C6pFnQlHRiOqYWZCvGk7hAAigOPn0KM+ceVrfMJIh Wx+eLZK1LPbH5sHwLT6jvuB6N5doKxwIk9zJ9D27UCkuFKtcCXkZEGK6IP9vsgiRd6PY +vAyLm78Erpwe80GAkrcKp6XFH2/0pnrRpgtGOq18jJ2WVUM8lq6tIK52CAja+oC1URH y3pAwnJ6zRYnH+Ns1BwaSULisYh9fW+GY2DEGVH8jxzYCiDoiTbsqIDVlVpbSKqKGjql d7G9G9RmtSluBC+AYwnienO0DAcao06zT78Rfb4BVzYlknPwSvSjjnx8hecfXAHEUSBu GzBQ== X-Gm-Message-State: AGRZ1gJdxbEPz1yE4ff43qtltBSSxxKucXQMJ2OG6zOwZuCYmmuLfyDW N/MIGWtIJO1NRSmeHXxdCHgPoUGq3FATvQnrFALO7w== X-Received: by 2002:a19:41c4:: with SMTP id o187mr1800325lfa.32.1540901305574; Tue, 30 Oct 2018 05:08:25 -0700 (PDT) MIME-Version: 1.0 References: <20181017213012.233957-1-kunyi@google.com> <20181017213012.233957-3-kunyi@google.com> In-Reply-To: <20181017213012.233957-3-kunyi@google.com> From: Linus Walleij Date: Tue, 30 Oct 2018 13:08:14 +0100 Message-ID: Subject: Re: [PATCH 2/2] pinctrl: pinctrl-npcm7xx: Set BGPIOF_VOLATILE_REG To: kunyi@google.com Cc: "open list:GPIO SUBSYSTEM" , Tomer Maimon , "linux-kernel@vger.kernel.org" , avifishman70@gmail.com, OpenBMC Maillist , Mark Brown Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 17, 2018 at 11:30 PM Kun Yi wrote: > Indicate that the pins are both controlled by the pinctrl driver and the > generic GPIO driver, thus GPIO driver should read the register value > before updating, instead of using the stored shadow register values. > > Signed-off-by: Kun Yi This is quite a rough measure, if we instead use regmap-mmio we can exercise fine control over what register are volatile and not instead of saying that all of them or some of them are. Yours, Linus Walleij