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Date:   Thu, 01 Nov 2018 09:17:16 -0700 (PDT)
Subject:     Re: [PATCH 0/3] RISC-V: A few build/warning fixes and cleanup
In-Reply-To: <da34ca57-ea7b-7fb9-bc45-4b315513e43f@deltatee.com>
CC:     philip.li@intel.com, fengguang.wu@intel.com, aou@eecs.berkeley.edu,
        lkp@intel.com, kbuild@lists.01.org, zongbox@gmail.com,
        linux-kernel@vger.kernel.org, Olof Johansson <olof@lixom.net>,
        linux-riscv@lists.infradead.org
From:   Palmer Dabbelt <palmer@sifive.com>
To:     logang@deltatee.com
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On Thu, 01 Nov 2018 08:43:15 PDT (-0700), logang@deltatee.com wrote:
>
>
> On 2018-10-31 8:19 p.m., Li, Philip wrote:
>>>> I think it would also be very nice to get the existing kbuild test robot
>>>> to start compile testing a few riscv configs. It already does most of
>> thanks Logan, the support to riscv and nds32 has been in our TODO list for
>> a while, but whole team is blocked by other effort. We will focus on this soon
>> to complete it within 2-3 weeks.
>
> Thanks! Glad to hear it.

We should probably at least have builds for rv32imac, rv32imafdc, rv64imac, and 
rv64imafdc.  It's probably also good to test SMP/non-SMP as well as 
medlow/medany, as I doubt those get regularly tested.  If you'd like I can 
write up the configs, just point me to something that describes what I should 
do.