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[209.85.208.181]) by smtp.gmail.com with ESMTPSA id n3-v6sm4773594lfe.8.2018.11.01.10.11.21 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Nov 2018 10:11:22 -0700 (PDT) Received: by mail-lj1-f181.google.com with SMTP id x85-v6so14511834ljb.2 for ; Thu, 01 Nov 2018 10:11:21 -0700 (PDT) X-Received: by 2002:a2e:12c1:: with SMTP id 62-v6mr5955225ljs.74.1541092280983; Thu, 01 Nov 2018 10:11:20 -0700 (PDT) MIME-Version: 1.0 References: <1541073999-11752-1-git-send-email-vbadigan@codeaurora.org> <1541073999-11752-3-git-send-email-vbadigan@codeaurora.org> In-Reply-To: <1541073999-11752-3-git-send-email-vbadigan@codeaurora.org> From: Evan Green Date: Thu, 1 Nov 2018 10:10:44 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH V3 2/2] mmc: sdhci-msm: Re-initialize DLL if MCLK is gated dynamically To: vbadigan@codeaurora.org Cc: adrian.hunter@intel.com, Ulf Hansson , robh+dt@kernel.org, Doug Anderson , asutoshd@codeaurora.org, riteshh@codeaurora.org, stummala@codeaurora.org, sayali , linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 1, 2018 at 5:08 AM Veerabhadrarao Badiganti wrote: > > On few SDHCI-MSM controllers, the host controller's clock tuning > circuit may go out of sync if controller clocks are gated which > eventually will result in data CRC, command CRC/timeout errors. > To overcome this h/w limitation, the DLL needs to be re-initialized > and restored with its old settings once clocks are ungated. > > Signed-off-by: Veerabhadrarao Badiganti > --- > drivers/mmc/host/sdhci-msm.c | 59 ++++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 57 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c Reviewed-by: Evan Green