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[209.132.180.67]) by mx.google.com with ESMTP id e73-v6si35326267pfb.98.2018.11.02.13.34.31; Fri, 02 Nov 2018 13:34:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b="nMVF/ayN"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=wdc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727719AbeKCFmo (ORCPT + 99 others); Sat, 3 Nov 2018 01:42:44 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:7957 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726041AbeKCFmn (ORCPT ); Sat, 3 Nov 2018 01:42:43 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1541190872; x=1572726872; h=subject:to:cc:references:from:message-id:date: mime-version:in-reply-to:content-transfer-encoding; bh=pW4aDx5pzVmJiBqjnCTvIlhWDrIUp+KXcHKEyjPl4kk=; b=nMVF/ayNlVipyzki7CaBmYc2ckypGROeEsOLGkKh4hh1R2WgIcrf8s0Y uQvRbi5z/NUfv/J9oQ7jc8cbatro0EoBzA5Z1lzkmainWFMoxKhlb/dPO pYQH0WoFqjg7SocZpQeOX7PXaxjERE+mRpUFXC5ZVXCAzXvqgkYPrWCkv qn4e3ku/90D5vbHL2rp7qFvJc5aUkRLoWnzyxjsAZTpLE80ByDmlJS4Wr ioTWUrxTbQGXXXrnT7TPrO2iIuc/LjZuKa21wU9CLN3X3zBuloWFrly7t 1lW7nEbljcNFbAnbOLuB5d8RnevFndXGrFXZBiRyndkN33kE5KGckW9aX A==; X-IronPort-AV: E=Sophos;i="5.54,457,1534780800"; d="scan'208";a="191156188" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 03 Nov 2018 04:34:31 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 02 Nov 2018 13:18:01 -0700 Received: from c02v91rdhtd5.sdcorp.global.sandisk.com (HELO [10.111.69.187]) ([10.111.69.187]) by uls-op-cesaip02.wdc.com with ESMTP; 02 Nov 2018 13:34:07 -0700 Subject: Re: [RFC 1/2] dt-bindings: topology: Add RISC-V cpu topology. To: Rob Herring Cc: "linux-riscv@lists.infradead.org" , Palmer Dabbelt , Anup Patel , Christoph Hellwig , Damien Le Moal , Thomas Gleixner , Mark Rutland , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "alankao@andestech.com" , Zong Li References: <1541113468-22097-1-git-send-email-atish.patra@wdc.com> <1541113468-22097-2-git-send-email-atish.patra@wdc.com> From: Atish Patra Message-ID: <954ec7be-f7ba-4e00-70fe-130cb4b84e61@wdc.com> Date: Fri, 2 Nov 2018 13:34:06 -0700 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/2/18 6:09 AM, Rob Herring wrote: > On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote: >> >> Define a RISC-V cpu topology. This is based on cpu-map in ARM world. >> But it doesn't need a separate thread node for defining SMT systems. >> Multiple cpu phandle properties can be parsed to identify the sibling >> hardware threads. Moreover, we do not have cluster concept in RISC-V. >> So package is a better word choice than cluster for RISC-V. > > There was a proposal to add package info for ARM recently. Not sure > what happened to that, but we don't need 2 different ways. > > There's never going to be clusters for RISC-V? What prevents that? > Seems shortsighted to me. > Agreed. My intention was to keep it simple at first go. If package node is added, that would work for us as well. >> >> Signed-off-by: Atish Patra >> --- >> .../devicetree/bindings/riscv/topology.txt | 154 +++++++++++++++++++++ >> 1 file changed, 154 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/riscv/topology.txt >> >> diff --git a/Documentation/devicetree/bindings/riscv/topology.txt b/Documentation/devicetree/bindings/riscv/topology.txt >> new file mode 100644 >> index 00000000..96039ed3 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/riscv/topology.txt >> @@ -0,0 +1,154 @@ >> +=========================================== >> +RISC-V cpu topology binding description >> +=========================================== >> + >> +=========================================== >> +1 - Introduction >> +=========================================== >> + >> +In a RISC-V system, the hierarchy of CPUs can be defined through following nodes that >> +are used to describe the layout of physical CPUs in the system: >> + >> +- packages >> +- core >> + >> +The cpu nodes (bindings defined in [1]) represent the devices that >> +correspond to physical CPUs and are to be mapped to the hierarchy levels. >> +Simultaneous multi-threading (SMT) systems can also represent their topology >> +by defining multiple cpu phandles inside core node. The details are explained >> +in paragraph 3. > > I don't see a reason to do this differently than ARM. That said, I > don't think the thread part is in use on ARM, so it could possibly be > changed. > >> + >> +The remainder of this document provides the topology bindings for ARM, based > > for ARM? > Sorry for the typo. >> +on the Devicetree Specification, available from: >> + >> +https://www.devicetree.org/specifications/ >> + >> +If not stated otherwise, whenever a reference to a cpu node phandle is made its >> +value must point to a cpu node compliant with the cpu node bindings as >> +documented in [1]. >> +A topology description containing phandles to cpu nodes that are not compliant >> +with bindings standardized in [1] is therefore considered invalid. >> + >> +This cpu topology binding description is mostly based on the topology defined >> +in ARM [2]. >> +=========================================== >> +2 - cpu-topology node > > cpu-map. Why change this? > To my ears, it felt a better name. But I don't mind dropping it in favor of cpu-map if we are going to standardize cpu-map for both ARM & RISC-V. > What I would like to see is the ARM topology binding reworked to be > common or some good reasons why it doesn't work for RISC-V as-is. > IMHO, ARM topology can be reworked and put it in a common place so that RISC-V can leverage that. My intention for this RFC patch was to start the ball rolling on cpu topology in RISC-V and see if DT approach is fine with everybody. I would be happy to see ARM code to move it to a common code base where RISC-V can reuse it. Regards, Atish > Rob >