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[209.132.180.67]) by mx.google.com with ESMTP id 1-v6si44356666plr.113.2018.11.05.06.12.11; Mon, 05 Nov 2018 06:12:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730013AbeKEX3e (ORCPT + 99 others); Mon, 5 Nov 2018 18:29:34 -0500 Received: from mga01.intel.com ([192.55.52.88]:53845 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728718AbeKEX3d (ORCPT ); Mon, 5 Nov 2018 18:29:33 -0500 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Nov 2018 06:09:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,468,1534834800"; d="scan'208,223";a="93781803" Received: from jsakkine-mobl1.tm.intel.com (HELO localhost) ([10.237.50.180]) by FMSMGA003.fm.intel.com with ESMTP; 05 Nov 2018 06:09:33 -0800 Date: Mon, 5 Nov 2018 16:09:33 +0200 From: Jarkko Sakkinen To: Andy Shevchenko Cc: "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , Platform Driver , linux-sgx@vger.kernel.org, Dave Hansen , sean.j.christopherson@intel.com, nhorman@redhat.com, npmccallum@redhat.com, serge.ayoun@intel.com, shay.katz-zamir@intel.com, haitao.huang@intel.com, mark.shanahan@intel.com, Andy Shevchenko , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Konrad Rzeszutek Wilk , David Woodhouse , davidwang@zhaoxin.com, "Kirill A. Shutemov" , "Levin, Alexander (Sasha Levin)" , qianyue.zj@alibaba-inc.com, Linux Kernel Mailing List Subject: Re: [PATCH v15 05/23] x86/cpu/intel: Detect SGX support and update caps appropriately Message-ID: <20181105140933.GA24038@linux.intel.com> References: <20181102231320.29164-1-jarkko.sakkinen@linux.intel.com> <20181102231320.29164-6-jarkko.sakkinen@linux.intel.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="qMm9M+Fa2AknHoGS" Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --qMm9M+Fa2AknHoGS Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sat, Nov 03, 2018 at 03:05:39PM +0200, Andy Shevchenko wrote: > > +static void detect_sgx(struct cpuinfo_x86 *c) > > +{ > > + bool unsupported = false; > > + unsigned long long fc; > > + > > + rdmsrl(MSR_IA32_FEATURE_CONTROL, fc); > > + if (!(fc & FEATURE_CONTROL_LOCKED)) { > > + pr_err_once("sgx: IA32_FEATURE_CONTROL MSR is not locked\n"); > > + unsupported = true; > > + } else if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) { > > + pr_err_once("sgx: not enabled in IA32_FEATURE_CONTROL MSR\n"); > > + unsupported = true; > > + } else if (!cpu_has(c, X86_FEATURE_SGX1)) { > > + pr_err_once("sgx: SGX1 instruction set not supported\n"); > > + unsupported = true; > > + } > > If you do > > } else { > /* Supported */ > return; > } Agree. Would this be a more clean flow in the attached patch? /Jarkko --qMm9M+Fa2AknHoGS Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="0001-x86-cpu-intel-clean-up-detect_sgx-flow.patch" From 3b863a7db00cefffc15df918a5132c35ea313c27 Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 5 Nov 2018 16:06:06 +0200 Subject: [PATCH] x86/cpu/intel: clean up detect_sgx() flow Signed-off-by: Jarkko Sakkinen --- arch/x86/kernel/cpu/intel.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index bc52c52f7025..8a20a193d399 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -598,28 +598,36 @@ static void detect_tme(struct cpuinfo_x86 *c) static void detect_sgx(struct cpuinfo_x86 *c) { - bool unsupported = false; unsigned long long fc; rdmsrl(MSR_IA32_FEATURE_CONTROL, fc); if (!(fc & FEATURE_CONTROL_LOCKED)) { pr_err_once("sgx: IA32_FEATURE_CONTROL MSR is not locked\n"); - unsupported = true; - } else if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) { + goto out_unsupported; + } + + if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) { pr_err_once("sgx: not enabled in IA32_FEATURE_CONTROL MSR\n"); - unsupported = true; - } else if (!cpu_has(c, X86_FEATURE_SGX1)) { + goto out_unsupported; + } + + if (!cpu_has(c, X86_FEATURE_SGX1)) { pr_err_once("sgx: SGX1 instruction set not supported\n"); - unsupported = true; + goto out_unsupported; } - if (unsupported) { - setup_clear_cpu_cap(X86_FEATURE_SGX); - setup_clear_cpu_cap(X86_FEATURE_SGX1); - setup_clear_cpu_cap(X86_FEATURE_SGX2); + if (!(fc & FEATURE_CONTROL_SGX_LE_WR)) { + pr_info_once("sgx: launch control MSRs are not writable\n"); + goto out_msrs_rdonly; } - if (unsupported || !(fc & FEATURE_CONTROL_SGX_LE_WR)) - setup_clear_cpu_cap(X86_FEATURE_SGX_LC); + + return; +out_unsupported: + setup_clear_cpu_cap(X86_FEATURE_SGX); + setup_clear_cpu_cap(X86_FEATURE_SGX1); + setup_clear_cpu_cap(X86_FEATURE_SGX2); +out_msrs_rdonly: + setup_clear_cpu_cap(X86_FEATURE_SGX_LC); } static void init_intel_energy_perf(struct cpuinfo_x86 *c) -- 2.19.1 --qMm9M+Fa2AknHoGS--