Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp1497082imu; Mon, 5 Nov 2018 22:46:08 -0800 (PST) X-Google-Smtp-Source: AJdET5dj1PGz6GbsTVJujL3BMI+ZxOV1iNqU7GbP0xP/0gNgSEr38dODTRAEBsmlrnX9R2RMdwLQ X-Received: by 2002:a62:cc4:: with SMTP id 65-v6mr24996239pfm.127.1541486768903; Mon, 05 Nov 2018 22:46:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541486768; cv=none; d=google.com; s=arc-20160816; b=VRZuCKvep03MOmVJHpIvuMGqcz2IlzALSJB55lXa22a537Tna364lJsMtR2sF1xxtt snQdTH9ylRPopePt5nXf+yC6Gq34XldXQwb+D3KHc7kMxyW6ITQUDD+fOJqG2WrkVESy zBgZysc+8711UFpfem/9LgRfNCQzOZXyv/ADvzYs1ya0GXj3H4LpyQU9yce46rQPGhPN 5LCsgrNlaYmrznPD6PYQ2DhnB5HNrRWfS88vTdaVO+GPfnsnKFL4nOVq/zNAGv5jrEn3 q1KzWFsd9fzvVOOPXHGPKtzlJhxQo/gvW72+afMPjTZFQ65KH3lat6Qmn/htYx69VSHd hHhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=X37dYZmH70cs98hXE6Elo6/1jGY7vbw37+/rK59Z5Y8=; b=Rbs5x56oY0fet1MNN+W9tkFjnbg3lwbabKKPU8vNuzsKegFV4ATrpL4d1QrRd0ZR8G wkjP+ce9hRyCpkpt5RxYCBb0QpTus5qLfPBPc7q4AgaaGnhD4tKF1o1MkyAI7Za5o1nj tIG88sIMWJIRVIBUkAeifygUTrctQ4c4Lf16g968DQ0KQFgM/9uzZ3FrAPobX8iDHTJF TfY6iPOliExrdAFBmXlsV0UE3EjQz2gIz8Cbq8TzbVL74w1C7H5iCw9UOLIU1fqdu4q6 J0Nl1AOEn2yEnvGYHbYy/Z/W+x9iG72J/A0SAEMYPKVmM2UOj/R/Gi27NQNNq+wNgIhZ qgLA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 88-v6si14066964plc.34.2018.11.05.22.45.53; Mon, 05 Nov 2018 22:46:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387969AbeKFQHE (ORCPT + 99 others); Tue, 6 Nov 2018 11:07:04 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:56427 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2387649AbeKFQGN (ORCPT ); Tue, 6 Nov 2018 11:06:13 -0500 X-UUID: cf2fd36573ad455298853a169057e97b-20181106 X-UUID: cf2fd36573ad455298853a169057e97b-20181106 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1874491118; Tue, 06 Nov 2018 14:42:24 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 6 Nov 2018 14:42:22 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 6 Nov 2018 14:42:22 +0800 From: Weiyi Lu To: Matthias Brugger , Stephen Boyd , Rob Herring CC: James Liao , Fan Chen , , , , , , Weiyi Lu , Owen Chen Subject: [PATCH v1 02/11] clk: mediatek: add new member to mtk_pll_data Date: Tue, 6 Nov 2018 14:41:57 +0800 Message-ID: <20181106064206.17535-4-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181106064206.17535-1-weiyi.lu@mediatek.com> References: <20181106064206.17535-1-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Owen Chen 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits, add a variable to indicate this change and backward-compatible. 2. fmin: The pll freqency lower-bound is vary from 1GMhz to 1.5Ghz, add a variable to indicate platform-dependent. Signed-off-by: Owen Chen --- drivers/clk/mediatek/clk-mtk.h | 2 ++ drivers/clk/mediatek/clk-pll.c | 10 +++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f83c2bbb677e..1882221fe994 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -215,7 +215,9 @@ struct mtk_pll_data { const struct clk_ops *ops; u32 rst_bar_mask; unsigned long fmax; + unsigned long fmin; int pcwbits; + int pcwibits; uint32_t pcw_reg; int pcw_shift; const struct mtk_pll_div_table *div_table; diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index f54e4015b0b1..0ec2c62d9383 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -69,11 +69,13 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, { int pcwbits = pll->data->pcwbits; int pcwfbits; + int ibits; u64 vco; u8 c = 0; /* The fractional part of the PLL divider. */ - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; + pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0; vco = (u64)fin * pcw; @@ -138,9 +140,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, u32 freq, u32 fin) { - unsigned long fmin = 1000 * MHZ; + unsigned long fmin = pll->data->fmin ? pll->data->fmin : 1000 * MHZ; const struct mtk_pll_div_table *div_table = pll->data->div_table; u64 _pcw; + int ibits; u32 val; if (freq > pll->data->fmax) @@ -164,7 +167,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, } /* _pcw = freq * postdiv / fin * 2^pcwfbits */ - _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS); + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; + _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits); do_div(_pcw, fin); *pcw = (u32)_pcw; -- 2.18.0