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Date:   Tue, 6 Nov 2018 14:11:19 +0100
From:   Peter Zijlstra <peterz@infradead.org>
To:     Nadav Amit <namit@vmware.com>
Cc:     Ingo Molnar <mingo@redhat.com>,
        LKML <linux-kernel@vger.kernel.org>, X86 ML <x86@kernel.org>,
        "H. Peter Anvin" <hpa@zytor.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Borislav Petkov <bp@alien8.de>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Andy Lutomirski <luto@kernel.org>,
        Kees Cook <keescook@chromium.org>,
        Dave Hansen <dave.hansen@intel.com>,
        Masami Hiramatsu <mhiramat@kernel.org>
Subject: Re: [PATCH v3 6/7] x86/alternatives: use temporary mm for text poking
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On Tue, Nov 06, 2018 at 09:20:19AM +0100, Peter Zijlstra wrote:

> By our current way of thinking, kmap_atomic simply is not correct.

Something like the below; which weirdly builds an x86_32 kernel.
Although I imagine a very sad one.

---

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index ba7e3464ee92..e273f3879d04 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1449,6 +1449,16 @@ config PAGE_OFFSET
 config HIGHMEM
 	def_bool y
 	depends on X86_32 && (HIGHMEM64G || HIGHMEM4G)
+	depends on !SMP || BROKEN
+	help
+	  By current thinking kmap_atomic() is broken, since it relies on per
+	  CPU PTEs in the global (kernel) address space and relies on CPU local
+	  TLB invalidates to completely invalidate these PTEs. However there is
+	  nothing that guarantees other CPUs will not speculatively touch upon
+	  'our' fixmap PTEs and load then into their TLBs, after which our
+	  local TLB invalidate will not invalidate them.
+
+	  There are AMD chips that will #MC on inconsistent TLB states.
 
 config X86_PAE
 	bool "PAE (Physical Address Extension) Support"