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[209.132.180.67]) by mx.google.com with ESMTP id c5-v6si15838249plr.1.2018.11.06.18.14.03; Tue, 06 Nov 2018 18:14:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389134AbeKGLlm (ORCPT + 99 others); Wed, 7 Nov 2018 06:41:42 -0500 Received: from mail-sz2.amlogic.com ([211.162.65.114]:8261 "EHLO mail-sz2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388677AbeKGLlm (ORCPT ); Wed, 7 Nov 2018 06:41:42 -0500 Received: from [10.28.18.137] (10.28.18.137) by mail-sz2.amlogic.com (10.28.11.6) with Microsoft SMTP Server (TLS) id 15.0.1320.4; Wed, 7 Nov 2018 10:13:26 +0800 Subject: Re: [PATCH v6 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller To: Boris Brezillon CC: Jianxin Pan , , Yixun Lan , David Woodhouse , Brian Norris , Marek Vasut , Richard Weinberger , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Carlo Caione , Kevin Hilman , Rob Herring , Jian Hu , Hanjie Lin , Victor Wan , , , References: <1541090542-19618-1-git-send-email-jianxin.pan@amlogic.com> <1541090542-19618-3-git-send-email-jianxin.pan@amlogic.com> <20181105165321.7ea2b45f@bbrezillon> <20181106102851.61deb97a@bbrezillon> <20181106112206.65a70a81@bbrezillon> <99475361-0115-7c16-3b7e-8f0d3a779446@amlogic.com> <20181106171655.3808d8eb@bbrezillon> From: Liang Yang Message-ID: Date: Wed, 7 Nov 2018 10:13:26 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <20181106171655.3808d8eb@bbrezillon> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.28.18.137] X-ClientProxiedBy: mail-sz2.amlogic.com (10.28.11.6) To mail-sz2.amlogic.com (10.28.11.6) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2018/11/7 0:16, Boris Brezillon wrote: > On Tue, 6 Nov 2018 19:08:27 +0800 > Liang Yang wrote: > >> On 2018/11/6 18:22, Boris Brezillon wrote: >>> On Tue, 6 Nov 2018 18:00:37 +0800 >>> Liang Yang wrote: >>> >>>> On 2018/11/6 17:28, Boris Brezillon wrote: >>>>> On Tue, 6 Nov 2018 17:08:00 +0800 >>>>> Liang Yang wrote: >>>>> >>>>>> On 2018/11/5 23:53, Boris Brezillon wrote: >>>>>>> On Fri, 2 Nov 2018 00:42:21 +0800 >>>>>>> Jianxin Pan wrote: >>>>>>> >>>>>>>> + >>>>>>>> +static inline u8 meson_nfc_read_byte(struct mtd_info *mtd) >>>>>>>> +{ >>>>>>>> + struct nand_chip *nand = mtd_to_nand(mtd); >>>>>>>> + struct meson_nfc *nfc = nand_get_controller_data(nand); >>>>>>>> + u32 cmd; >>>>>>>> + >>>>>>>> + cmd = nfc->param.chip_select | NFC_CMD_DRD | 0; >>>>>>>> + writel(cmd, nfc->reg_base + NFC_REG_CMD); >>>>>>>> + >>>>>>>> + meson_nfc_drain_cmd(nfc); >>>>>>> >>>>>>> You probably don't want to drain the FIFO every time you read a byte on >>>>>>> the bus, and I guess the INPUT FIFO is at least as big as the CMD >>>>>>> FIFO, right? If that's the case, you should queue as much DRD cmd as >>>>>>> possible and only sync when the user explicitly requests it or when >>>>>>> the INPUT/READ FIFO is full. >>>>>>> >>>>>> Register 'NFC_REG_BUF' can holds only 4 bytes, also DRD sends only one >>>>>> nand cycle to read one byte and covers the 1st byte every time reading. >>>>>> i think nfc controller is faster than nand cycle, but really it is not >>>>>> high efficiency when reading so many bytes once. >>>>>> Or use dma command here like read_page and read_page_raw. >>>>> >>>>> Yep, that's also an alternative, though you'll have to make sure the >>>>> buffer passed through the nand_op_inst is DMA-safe, and use a bounce >>>>> buffer when that's not the case. >>>>> >>>> ok, i will try dma here. >>> >>> We should probably expose the bounce buf handling as generic helpers at >>> the rawnand level: >>> >>> void *nand_op_get_dma_safe_input_buf(struct nand_op_instr *instr) >>> { >>> void *buf; >>> >>> if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR)) >>> return NULL; >>> >>> if (virt_addr_valid(instr->data.in) && >>> !object_is_on_stack(instr->data.buf.in)) >>> return instr->data.buf.in; >>> >>> return kzalloc(instr->data.len, GFP_KERNEL); >>> } >>> >>> void nand_op_put_dma_safe_input_buf(struct nand_op_instr *instr, >>> void *buf) >>> { >>> if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR) || >>> WARN_ON(!buf)) >>> return; >>> >>> if (buf == instr->data.buf.in) >>> return; >>> >>> memcpy(instr->data.buf.in, buf, instr->data.len); >>> kfree(buf); >>> } >>> >>> const void *nand_op_get_dma_safe_output_buf(struct nand_op_instr *instr) >>> { >>> void *buf; >>> >>> if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR)) >>> return NULL; >>> >>> if (virt_addr_valid(instr->data.out) && >>> !object_is_on_stack(instr->data.buf.out)) >>> return instr->data.buf.out; >>> >>> return kmemdup(instr->data.buf.out, GFP_KERNEL); >>> } >>> >>> void nand_op_put_dma_safe_output_buf(struct nand_op_instr *instr, >>> void *buf) >>> { >>> if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR) || >>> WARN_ON(!buf)) >>> return; >>> >>> if (buf != instr->data.buf.out) >>> kfree(buf); >>> } >>> >> >> that is more convenient. >> i will use meson_chip->databuf as the bounce mid-buffer now. > > It won't work: the bounce buffer is allocated after the detection, and > the detection code is calling ->exec_op(). > > Just add a new patch to you series adding these helpers to nand_base.c. > ok > . >