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[209.132.180.67]) by mx.google.com with ESMTP id l26-v6si21367910pfe.21.2018.11.06.19.31.45; Tue, 06 Nov 2018 19:32:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Gx2T63Ck; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731066AbeKGMw2 (ORCPT + 99 others); Wed, 7 Nov 2018 07:52:28 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:36895 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727315AbeKGMw2 (ORCPT ); Wed, 7 Nov 2018 07:52:28 -0500 Received: by mail-wr1-f67.google.com with SMTP id o15-v6so12181383wrv.4 for ; Tue, 06 Nov 2018 19:23:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=ImL7x6tAbC9KafSE4YGoOInmvHYlXGIZ1JlveBOmkbo=; b=Gx2T63CkCd4Maku8kUN6V1oVH90ojCVFPO2hCUFg4qVkMMHQaLFC5349fBRm7T8W/D R8HyEgqzTPVa29hWvf4mURAlnKUS82pjmAXmyVZ6uDXTj8V1fLN4kS++Td9AF2aIZ+OI H0BwgFI9L+Vi5ZyYQG4gLzflH59U6VFH6KKiA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=ImL7x6tAbC9KafSE4YGoOInmvHYlXGIZ1JlveBOmkbo=; b=hNWuZReNI7A0EHrV2SRnKIDvJhc08nLdCCt8zMT70ZaA9qfD95MZBzUCVSktUlJMjy nUOepaVcPMnEKKVcLkfmKOO8vlgeDqQc88kpHweCb7HnrYQAPRCRI7rLujv+oQi9NPw7 vXIhU2mG+M5wENFyFAtXLFHfD4VDHon8zekdhevRVYY0ubUXVqhQJSlFWURYSG/kapRV l9w4IFN06AAguJQMGrMwMrsujZfH8vUO/vL3Zu8lGgvuWQkGjp3SfLFix8VbVSkbphW3 ZUVF7Z6zFnlS+GsAfF0BBO6fw4Ib41u6tmjzJXznLK/82KdZQsQt/RRYjgJmwDoiiPBP DMEg== X-Gm-Message-State: AGRZ1gKHH/13bIWI5RTc47Vda9ltFFDMoy2fPqX9xBmH8bNXWrWh7xDe WqGd9vfE8bnEaGnBiKsP0EgGDDW1h7mOxX2R X-Received: by 2002:a05:6000:110b:: with SMTP id z11mr153001wrw.136.1541561038168; Tue, 06 Nov 2018 19:23:58 -0800 (PST) Received: from leoy-ThinkPad-X240s ([209.250.228.18]) by smtp.gmail.com with ESMTPSA id t198-v6sm6187002wmd.9.2018.11.06.19.23.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Nov 2018 19:23:57 -0800 (PST) Date: Wed, 7 Nov 2018 11:23:50 +0800 From: leo.yan@linaro.org To: Mathieu Poirier Cc: linux-arm-kernel@lists.infradead.org, alexander.shishkin@linux.intel.com, suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] coresight: etm3x: Release CLAIM tag when operated from perf Message-ID: <20181107032350.GH3983@leoy-ThinkPad-X240s> References: <1541456790-28282-1-git-send-email-mathieu.poirier@linaro.org> <1541456790-28282-4-git-send-email-mathieu.poirier@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1541456790-28282-4-git-send-email-mathieu.poirier@linaro.org> User-Agent: Mutt/1.10+31 (9cdd884) (2018-06-19) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mathieu, On Mon, Nov 05, 2018 at 03:26:30PM -0700, Mathieu Poirier wrote: > This patch deals with the release of the CLAIM tag when the ETM is > operated from perf. Otherwise the tag is left asserted and subsequent > requests to use the device fail. > > Signed-off-by: Mathieu Poirier > --- > drivers/hwtracing/coresight/coresight-etm3x.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c > index fd5c4cca7db5..000796394662 100644 > --- a/drivers/hwtracing/coresight/coresight-etm3x.c > +++ b/drivers/hwtracing/coresight/coresight-etm3x.c > @@ -603,6 +603,8 @@ static void etm_disable_perf(struct coresight_device *csdev) > */ > etm_set_pwrdwn(drvdata); > > + coresight_disclaim_device_unlocked(drvdata->base); > + Just remind, this isn't consistent with the sequency in function etm_disable_hw(), which has the reversed sequence between etm_set_pwrdwn() and coresight_disclaim_device_unlocked(). Not sure which one sequence is more suitable, at the first glance, accessing register after pwrdwn related operation might have risk for deadlock? Thanks, Leo Yan > CS_LOCK(drvdata->base); > } > > -- > 2.7.4 >