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[209.132.180.67]) by mx.google.com with ESMTP id o9-v6si410569pfe.283.2018.11.07.04.03.33; Wed, 07 Nov 2018 04:03:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730598AbeKGVc1 (ORCPT + 99 others); Wed, 7 Nov 2018 16:32:27 -0500 Received: from smtp.ctxuk.citrix.com ([185.25.65.24]:2722 "EHLO SMTP.EU.CITRIX.COM" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726725AbeKGVc0 (ORCPT ); Wed, 7 Nov 2018 16:32:26 -0500 X-IronPort-AV: E=Sophos;i="5.54,475,1534809600"; d="scan'208";a="81521677" Subject: Re: [Xen-devel] [PATCH] x86/xen: fix pv boot From: Andrew Cooper To: Juergen Gross , , , CC: , , , , , References: <20181107113017.30090-1-jgross@suse.com> Openpgp: preference=signencrypt Autocrypt: addr=andrew.cooper3@citrix.com; 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Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Content-Language: en-GB X-ClientProxiedBy: AMSPEX02CAS02.citrite.net (10.69.22.113) To AMSPEX02CL02.citrite.net (10.69.22.126) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/11/18 11:55, Andrew Cooper wrote: > On 07/11/18 11:30, Juergen Gross wrote: >> + return ret; >> } >> >> static inline int xen_safe_read_ulong(unsigned long *addr, unsigned long *val) >> { >> - return __get_user(*val, (unsigned long __user *)addr); >> + int ret = 0; >> + unsigned long rval; >> + >> + asm volatile("1: mov"__i" %2,%"__r"1\n" >> + "2:\n" >> + ".section .fixup,\"ax\"\n" >> + "3: mov %3,%0\n" >> + " jmp 2b\n" >> + ".previous\n" >> + _ASM_EXTABLE(1b, 3b) >> + : "=r" (ret), "=r" (rval) >> + : "m" (*addr), "i" (-1), "0" (ret)); >> + *val = rval; >> + return ret; > This also uses rval uninitialised if a fault occurs. > > Overall, how about: > > static inline int xen_safe_write_ulong(unsigned long *addr, unsigned > long val) > { >     int ret = 0; > >     asm volatile("1: mov %[val], %[ptr]\n" >                  "2:\n" >                  ".section .fixup, \"ax\"\n" >                  "3: mov %[err], %[ret]\n" Actually, if you want a shorter fixup path, `sub $1, %[ret]` would also do, and drop the [err] constraint. ~Andrew