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From:   Horia Geanta <horia.geanta@nxp.com>
To:     Roy Pledge <roy.pledge@nxp.com>,
        "stuyoder@gmail.com" <stuyoder@gmail.com>,
        Laurentiu Tudor <laurentiu.tudor@nxp.com>,
        Leo Li <leoyang.li@nxp.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>
CC:     Youri Querry <youri.querry_1@nxp.com>
Subject: Re: [PATCH v1 1/2] bus: mc-bus: Add support for mapping shareable
 portals
Thread-Topic: [PATCH v1 1/2] bus: mc-bus: Add support for mapping shareable
 portals
Thread-Index: AQHUcI+CI7M4OPexAEu1FDf5Bamt4w==
Date:   Wed, 7 Nov 2018 12:07:40 +0000
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References: <1540931418-10697-1-git-send-email-roy.pledge@nxp.com>
 <1540931418-10697-2-git-send-email-roy.pledge@nxp.com>
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On 10/30/2018 10:31 PM, Roy Pledge wrote:=0A=
> Starting with v5 of NXP QBMan devices the hardware supports using=0A=
> regular cacheable/shareable memory as the backing store for the=0A=
> portals.=0A=
> =0A=
> This patch adds support for the new portal mode by switching to=0A=
> use the DPRC get object region v2 command which returns both=0A=
> a base address and offset for the portal memory. The new portal=0A=
> region is identified as shareable through the addition of a new=0A=
> flag.=0A=
> =0A=
> Signed-off-by: Roy Pledge <roy.pledge@nxp.com>=0A=
> ---=0A=
>  drivers/bus/fsl-mc/dprc.c           |  3 ++-=0A=
>  drivers/bus/fsl-mc/fsl-mc-bus.c     | 14 ++++++++++++--=0A=
>  drivers/bus/fsl-mc/fsl-mc-private.h | 17 ++++++++++++++---=0A=
>  3 files changed, 28 insertions(+), 6 deletions(-)=0A=
> =0A=
> diff --git a/drivers/bus/fsl-mc/dprc.c b/drivers/bus/fsl-mc/dprc.c=0A=
> index 1c3f621..bde856d 100644=0A=
> --- a/drivers/bus/fsl-mc/dprc.c=0A=
> +++ b/drivers/bus/fsl-mc/dprc.c=0A=
> @@ -461,8 +461,9 @@ int dprc_get_obj_region(struct fsl_mc_io *mc_io,=0A=
>  =0A=
>  	/* retrieve response parameters */=0A=
>  	rsp_params =3D (struct dprc_rsp_get_obj_region *)cmd.params;=0A=
> -	region_desc->base_offset =3D le64_to_cpu(rsp_params->base_addr);=0A=
> +	region_desc->base_offset =3D le64_to_cpu(rsp_params->base_offset);=0A=
>  	region_desc->size =3D le32_to_cpu(rsp_params->size);=0A=
> +	region_desc->base_address =3D le64_to_cpu(rsp_params->base_addr);=0A=
>  =0A=
>  	return 0;=0A=
>  }=0A=
> diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-=
bus.c=0A=
> index f0404c6..25ad422 100644=0A=
> --- a/drivers/bus/fsl-mc/fsl-mc-bus.c=0A=
> +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c=0A=
> @@ -487,10 +487,18 @@ static int fsl_mc_device_get_mmio_regions(struct fs=
l_mc_device *mc_dev,=0A=
>  				"dprc_get_obj_region() failed: %d\n", error);=0A=
>  			goto error_cleanup_regions;=0A=
>  		}=0A=
> -=0A=
> -		error =3D translate_mc_addr(mc_dev, mc_region_type,=0A=
> +		/* Older MC only returned region offset and no base address=0A=
Nitpick: comment style is not consistent with existing code in fsl-mc.=0A=
=0A=
> +		 * If base address is in the region_desc use it otherwise=0A=
> +		 * revert to old mechanism=0A=
> +		 */=0A=
> +		if (region_desc.base_address)=0A=
> +			regions[i].start =3D region_desc.base_address +=0A=
> +						region_desc.base_offset;=0A=
> +		else=0A=
> +			error =3D translate_mc_addr(mc_dev, mc_region_type,=0A=
>  					  region_desc.base_offset,=0A=
>  					  &regions[i].start);=0A=
> +=0A=
>  		if (error < 0) {=0A=
>  			dev_err(parent_dev,=0A=
>  				"Invalid MC offset: %#x (for %s.%d\'s region %d)\n",=0A=
> @@ -504,6 +512,8 @@ static int fsl_mc_device_get_mmio_regions(struct fsl_=
mc_device *mc_dev,=0A=
>  		regions[i].flags =3D IORESOURCE_IO;=0A=
>  		if (region_desc.flags & DPRC_REGION_CACHEABLE)=0A=
>  			regions[i].flags |=3D IORESOURCE_CACHEABLE;=0A=
> +		if (region_desc.flags & DPRC_REGION_SHAREABLE)=0A=
> +			regions[i].flags |=3D IORESOURCE_MEM;=0A=
>  	}=0A=
>  =0A=
>  	mc_dev->regions =3D regions;=0A=
> diff --git a/drivers/bus/fsl-mc/fsl-mc-private.h b/drivers/bus/fsl-mc/fsl=
-mc-private.h=0A=
> index ea11b4f..28e40d1 100644=0A=
> --- a/drivers/bus/fsl-mc/fsl-mc-private.h=0A=
> +++ b/drivers/bus/fsl-mc/fsl-mc-private.h=0A=
> @@ -79,9 +79,11 @@ int dpmcp_reset(struct fsl_mc_io *mc_io,=0A=
>  =0A=
>  /* DPRC command versioning */=0A=
>  #define DPRC_CMD_BASE_VERSION			1=0A=
> +#define DPRC_CMD_2ND_VERSION			2=0A=
>  #define DPRC_CMD_ID_OFFSET			4=0A=
>  =0A=
>  #define DPRC_CMD(id)	(((id) << DPRC_CMD_ID_OFFSET) | DPRC_CMD_BASE_VERSI=
ON)=0A=
> +#define DPRC_CMD_V2(id)	(((id) << DPRC_CMD_ID_OFFSET) | DPRC_CMD_2ND_VER=
SION)=0A=
>  =0A=
>  /* DPRC command IDs */=0A=
>  #define DPRC_CMDID_CLOSE                        DPRC_CMD(0x800)=0A=
> @@ -99,7 +101,7 @@ int dpmcp_reset(struct fsl_mc_io *mc_io,=0A=
>  #define DPRC_CMDID_GET_CONT_ID                  DPRC_CMD(0x830)=0A=
>  #define DPRC_CMDID_GET_OBJ_COUNT                DPRC_CMD(0x159)=0A=
>  #define DPRC_CMDID_GET_OBJ                      DPRC_CMD(0x15A)=0A=
> -#define DPRC_CMDID_GET_OBJ_REG                  DPRC_CMD(0x15E)=0A=
> +#define DPRC_CMDID_GET_OBJ_REG                  DPRC_CMD_V2(0x15E)=0A=
>  #define DPRC_CMDID_SET_OBJ_IRQ                  DPRC_CMD(0x15F)=0A=
>  =0A=
>  struct dprc_cmd_open {=0A=
> @@ -199,9 +201,15 @@ struct dprc_rsp_get_obj_region {=0A=
>  	/* response word 0 */=0A=
>  	__le64 pad;=0A=
>  	/* response word 1 */=0A=
> -	__le64 base_addr;=0A=
> +	__le64 base_offset;=0A=
>  	/* response word 2 */=0A=
>  	__le32 size;=0A=
> +	u8 pad2[3];=0A=
Padding size (3B) is incorrect.=0A=
=0A=
Either add 4B of padding:=0A=
__le32 pad2;=0A=
=0A=
or expose the "type" field:=0A=
u8 type;=0A=
u8 pad2[3];=0A=
=0A=
> +	/* response word 3 */=0A=
> +	__le32 flags;=0A=
> +	__le32 pad3;=0A=
> +	/* response word 4 */=0A=
> +	__le64 base_addr;=0A=
>  };=0A=
>  =0A=
>  struct dprc_cmd_set_obj_irq {=0A=
> @@ -334,6 +342,7 @@ int dprc_set_obj_irq(struct fsl_mc_io *mc_io,=0A=
>  /* Region flags */=0A=
>  /* Cacheable - Indicates that region should be mapped as cacheable */=0A=
>  #define DPRC_REGION_CACHEABLE	0x00000001=0A=
> +#define DPRC_REGION_SHAREABLE	0x00000002=0A=
>  =0A=
The new flag should be added in documentation (DPAA2 UM).=0A=
=0A=
Regards,=0A=
Horia=0A=
=0A=