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[209.132.180.67]) by mx.google.com with ESMTP id r20-v6si455795pgm.28.2018.11.07.04.25.48; Wed, 07 Nov 2018 04:26:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731003AbeKGVxz convert rfc822-to-8bit (ORCPT + 99 others); Wed, 7 Nov 2018 16:53:55 -0500 Received: from mail.bootlin.com ([62.4.15.54]:55459 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726248AbeKGVxz (ORCPT ); Wed, 7 Nov 2018 16:53:55 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 733AB2072A; Wed, 7 Nov 2018 13:23:43 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from bbrezillon (aaubervilliers-681-1-93-44.w90-88.abo.wanadoo.fr [90.88.34.44]) by mail.bootlin.com (Postfix) with ESMTPSA id 201BE20510; Wed, 7 Nov 2018 13:23:43 +0100 (CET) Date: Wed, 7 Nov 2018 13:23:42 +0100 From: Boris Brezillon To: Christophe Kerello Cc: , , , , , , , , , , Subject: Re: [PATCH v2 2/3] mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver Message-ID: <20181107132342.33790247@bbrezillon> In-Reply-To: <70f99d79-a9d8-0651-d464-2d81b334dbfb@st.com> References: <1538732520-2800-1-git-send-email-christophe.kerello@st.com> <1538732520-2800-3-git-send-email-christophe.kerello@st.com> <20181105173905.385dd06e@bbrezillon> <70f99d79-a9d8-0651-d464-2d81b334dbfb@st.com> X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 7 Nov 2018 12:08:58 +0100 Christophe Kerello wrote: > >> + > >> +write_8bit: > >> + for (i = 0; i < len; i++) > >> + writeb_relaxed(p[i], io_addr_w); > > > > Is 8bit access really enforced by the byte accessor? In this case, how > > can you be sure 32-bit accesses are doing the right thing? Isn't there > > a bit somewhere in the config reg to configure the bus width? > > > > I have checked the framework after Miquèl comment sent on v1 => "If you > selected BOUNCE_BUFFER in the options, buf is supposedly > aligned, or am I missing something?". > > After checking the framework, my understanding was: > - In case of 8-bit access is requested, the framework provides no > guarantee on buf. To avoid any issue, I write byte per byte. > - In case of 8-bit access is not requested, it means that the > framework will try to write data in the page or in the oob. When writing > to oob, chip->oob_poi will be used and this buffer is aligned. When > writing to the page, as the driver enables NAND_USE_BOUNCE_BUFFER > option, buf is guarantee aligned. It's probably what happens right now, but there's no guarantee that all non-8-bit accesses will be provided a 32-bit aligned buffer. The only guarantee we provide is on buffer passed to the chip->ecc.read/write_xxx() hooks, and ->exec_op() can be used outside of the "page access" path. > > But, I agree that it would be safe to reconfigure the bus width in 8-bit > before writing byte per byte in case of a 16-bit NAND is used. Yes, and I also think you should not base your is-aligned check on the force_8bit value. Use IS_ALIGNED() instead.