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From:   Jean-Michel Hautbois <jhautbois@gmail.com>
Date:   Wed, 7 Nov 2018 18:07:42 +0100
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Subject: Re: sama5d: using the ebi interface from another driver
To:     ada@thorsis.com
Cc:     linux-arm-kernel@lists.infradead.org, boris.brezillon@bootlin.com,
        Nicolas Ferre <nicolas.ferre@atmel.com>,
        linux-kernel <linux-kernel@vger.kernel.org>
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Hi there !

Le mar. 6 nov. 2018 =C3=A0 10:57, Alexander Dahl <ada@thorsis.com> a =C3=A9=
crit :
>
> Hei hei,
>
> Am Freitag, 2. November 2018, 14:35:26 CET schrieb Jean-Michel Hautbois:
> > Then, after looking into deeper details in the datasheet I understand
> > it is connected through EBI and it sounds not so easy :D.
>
> Did you read docs on that? You'll find the binding docs here:
>
> Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt
>
> > I would appreciate some help/pointers on this, as there is (at least,
> > I could find) few documentation on how to use it except for NAND
> > cases.
>
> I use EBI with at91sam9g20 and custom FPGA on CS5 (0x6000000) and CS7
> (0x8000000).
>
> > I have something like that in my DTS, but not sure this is the correct
> > way to do it :
> >
> >         ebi: ebi@10000000 {
> >             pinctrl-0 =3D <&pinctrl_ebi_nand_addr>;
> >             pinctrl-names =3D "default";
> >             status =3D "okay";
> >
> >             dsp0: pef24628@1 {
> >                 status =3D "okay";
> >                 compatible =3D "intel,pef24628";
> >                 #address-cells =3D <1>;
> >                 #size-cells =3D <1>;
> >                 reg =3D <0x1 0x0 0x8000>;
> >                 pinctrl-0 =3D <&pinctrl_dsp_cs1>;
> >             };
> >
> >             dsp1: pef24628@2 {
> >                 status =3D "okay";
> >                 compatible =3D "intel,pef24628";
> >                 #address-cells =3D <1>;
> >                 #size-cells =3D <1>;
> >                 reg =3D <0x2 0x0 0x8000>;
> >                 pinctrl-0 =3D <&pinctrl_dsp_cs2>;
> >             };
>
> I'm not sure about those 'reg' settings. IIRC the first should correspond=
 to
> the CS line, on at91sam9g20 the 0x40000000 would be CS3 (which is used by
> NAND, like in the dts snippet you posted) and 0x50000000 would be CS4. Ar=
e CS1
> (which is used by SD-RAM) and CS2 free to use on sama5d3?
>
> Maybe that's different on sama5d3? I would check it again.

Well, yes, I am using CS1 and 2, and right now, I can confirm the reg
settings are ok as the platform_get_resource returns the correct
values :) !

> > The pinctrl for ebi should probably be changed however, I am wondering
> > how the (platform ?) driver can access the adress ? Should it parse
> > itself the parent, and find range, etc. Or is there an accessor for it
> > ?
>
> Probably. This is what I have for the at91sam9g20:
>
>             pinctrl@fffff400 {
>                 ebi {
>                     pinctrl_ebi_cs5: ebi-cs5-0 {
>                         atmel,pins =3D
>                             <AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_PULL_=
UP>;
>                     };
>
>                     pinctrl_ebi_cs7: ebi-cs7-0 {
>                         atmel,pins =3D
>                             <AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL=
_UP>;
>                     };
>
>                     pinctrl_ebi_nwait: ebi-nwait-0 {
>                         atmel,pins =3D
>                             <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL=
_UP>;
>                     };
>                 };
>             };
>
> > Maybe can I just manually toggle the CS GPIO, and don't try to make
> > anything more complex than what it should be ? The driver should not
> > be atmel dependant...
>
> As Ludovic said, you should check the settings and timings for the extern=
al
> memory interface. This could look more or less similar to that:
>
>             foo_bar: foo-bar@5,0 {
>                 status =3D "okay";
>                 pinctrl-0 =3D <&pinctrl_ebi_cs5>;
>                 pinctrl-names =3D "default";
>                 reg =3D <0x5 0x0 0x80000>;
>
>                 atmel,smc-bus-width =3D <8>;
>                 atmel,smc-read-mode =3D "nrd";
>                 atmel,smc-write-mode =3D "nwe";
>                 atmel,smc-exnw-mode =3D "ready";
>
>                 atmel,smc-ncs-rd-setup-ns =3D <7>;
>                 atmel,smc-nrd-setup-ns =3D <7>;
>                 atmel,smc-ncs-wr-setup-ns =3D <7>;
>                 atmel,smc-nwe-setup-ns =3D <7>;
>
>                 atmel,smc-ncs-rd-pulse-ns =3D <56>;
>                 atmel,smc-nrd-pulse-ns =3D <56>;
>                 atmel,smc-ncs-wr-pulse-ns =3D <56>;
>                 atmel,smc-nwe-pulse-ns =3D <56>;
>
>                 atmel,smc-nwe-cycle-ns =3D <77>;
>                 atmel,smc-nrd-cycle-ns =3D <77>;
>
>                 atmel,smc-tdf-ns =3D <0>;
>             };
>
> As you can see, quite a lot of settings are made, all depending on how th=
e
> memory access is supposed to be configured. You should look out for detai=
ls in
> the hardware manuals of the SoC and the devices you want to connect.

Yes, this is the last part I need to get information about, but this
is datasheet reading basically, so not a big deal :).
Thanks to both of you, Alexander and Ludovic, I have now something
really better ;).

JM