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From:   Abel Vesa <abel.vesa@nxp.com>
To:     Stephen Boyd <sboyd@kernel.org>
CC:     Andrey Smirnov <andrew.smirnov@gmail.com>,
        Anson Huang <anson.huang@nxp.com>,
        "A.s. Dong" <aisheng.dong@nxp.com>,
        Fabio Estevam <fabio.estevam@nxp.com>,
        Lucas Stach <l.stach@pengutronix.de>,
        Rob Herring <robh@kernel.org>,
        Sascha Hauer <kernel@pengutronix.de>,
        dl-linux-imx <linux-imx@nxp.com>, Abel Vesa <abelvesa@linux.com>,
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        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>,
        "open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v9 3/5] clk: imx: add SCCG PLL type
Thread-Topic: [PATCH v9 3/5] clk: imx: add SCCG PLL type
Thread-Index: AQHUU/MOgX3H5GYYv0SLPnYITk0b36Uj/uoAgCB6iACAAHccAIAAF9kA
Date:   Wed, 7 Nov 2018 20:26:25 +0000
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On Wed, Nov 07, 2018 at 11:01:02AM -0800, Stephen Boyd wrote:
> Quoting Abel Vesa (2018-11-07 03:54:45)
> > On Wed, Oct 17, 2018 at 12:55:52PM -0700, Stephen Boyd wrote:
> > > Quoting Abel Vesa (2018-09-24 03:39:55)
> > > > +static unsigned long clk_pll2_recalc_rate(struct clk_hw *hw,
> > > > +                                        unsigned long parent_rate)
> > > > +{
> > > > +       struct clk_sccg_pll *pll =3D to_clk_sccg_pll(hw);
> > > > +       u32 val, ref, divr1, divf1, divr2, divf2;
> > > > +       u64 temp64;
> > > > +
> > > > +       val =3D readl_relaxed(pll->base + PLL_CFG0);
> > > > +       switch (FIELD_GET(PLL_REF_MASK, val)) {
> > > > +       case 0:
> > > > +               ref =3D OSC_25M;
> > > > +               break;
> > > > +       case 1:
> > > > +               ref =3D OSC_27M;
> > > > +               break;
> > > > +       default:
> > > > +               ref =3D OSC_25M;
> > >=20
> > > Does this information not come through 'parent_rate'?
> > >=20
> >=20
> > No. So basically both pll1 and pll2 and the divider after it form toget=
her this SCCG:
> >=20
> > https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=3D834
> >=20
> > See: Figure 5-8. SSCG PLL Block Diagram
>=20
> Thanks for the link!
>=20
> >=20
> > We're basically reading the input of the pll 1 in order to compute the =
output of the entire SCCG.
> >=20
> > I know it's a mess. I'm working on cleaning it up, but for now we need =
this in in order to boot up.
>=20
> What's the plan to clean it up?

So I'm doing this in our internal tree first to make sure I don't break the
other (newer) socs.

I already have a prototype in testing but it's a long way to upstream it.

Basically, I'm replacing all of this with a single, more like a composite,
more complex, clock type that does all the magic inside.

One of the problems is the fact that the bypasses can have the same sources
and in my case, I'm implementing that as a list of parents name, but the
parent names list doesn't work with duplicates, so I have to find some othe=
r
way to do it.

Once I have something clean and tested enough I'll send it upstream.

>=20
> >=20
> > > > +               break;
> > > > +       }
> > > > +
> > > > +       val =3D readl_relaxed(pll->base + PLL_CFG2);
> > > > +       divr1 =3D FIELD_GET(PLL_DIVR1_MASK, val);
> > > > +       divr2 =3D FIELD_GET(PLL_DIVR2_MASK, val);
> > > > +       divf1 =3D FIELD_GET(PLL_DIVF1_MASK, val);
> > > > +       divf2 =3D FIELD_GET(PLL_DIVF2_MASK, val);
> > > > +
> > > > +       temp64 =3D ref * 2;
> > > > +       temp64 *=3D (divf1 + 1) * (divf2 + 1);
> > > > +
> > > > +       do_div(temp64, (divr1 + 1) * (divr2 + 1));
> > >=20
> > > Nitpicks: A comment with the equation may be helpful to newcomers.
> >=20
> > Since the SCCG is contructed by multiple different types of clocks here=
, the equation doesn't help
> > since it is spread in all constructing blocks.
>=20
> Ok.
>=20

-- =