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To:     Abel Vesa <abel.vesa@nxp.com>
From:   Stephen Boyd <sboyd@kernel.org>
In-Reply-To: <20181107202624.oya2runvbbwcilzu@fsr-ub1664-175>
Cc:     Andrey Smirnov <andrew.smirnov@gmail.com>,
        Anson Huang <anson.huang@nxp.com>,
        "A.s. Dong" <aisheng.dong@nxp.com>,
        Fabio Estevam <fabio.estevam@nxp.com>,
        Lucas Stach <l.stach@pengutronix.de>,
        Rob Herring <robh@kernel.org>,
        Sascha Hauer <kernel@pengutronix.de>,
        dl-linux-imx <linux-imx@nxp.com>, Abel Vesa <abelvesa@linux.com>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Michael Turquette <mturquette@baylibre.com>,
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        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>,
        "open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>
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Message-ID: <154163631513.88331.1765456171211364913@swboyd.mtv.corp.google.com>
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Subject: Re: [PATCH v9 3/5] clk: imx: add SCCG PLL type
Date:   Wed, 07 Nov 2018 16:18:35 -0800
Sender: linux-kernel-owner@vger.kernel.org
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Quoting Abel Vesa (2018-11-07 12:26:25)
> On Wed, Nov 07, 2018 at 11:01:02AM -0800, Stephen Boyd wrote:
> > =

> > =

> > What's the plan to clean it up?
> =

> So I'm doing this in our internal tree first to make sure I don't break t=
he
> other (newer) socs.
> =

> I already have a prototype in testing but it's a long way to upstream it.
> =

> Basically, I'm replacing all of this with a single, more like a composite,
> more complex, clock type that does all the magic inside.
> =

> One of the problems is the fact that the bypasses can have the same sourc=
es
> and in my case, I'm implementing that as a list of parents name, but the
> parent names list doesn't work with duplicates, so I have to find some ot=
her
> way to do it.
> =

> Once I have something clean and tested enough I'll send it upstream.

Ok. Thanks for the info.