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[209.132.180.67]) by mx.google.com with ESMTP id h3-v6si4694326pfd.228.2018.11.08.07.55.30; Thu, 08 Nov 2018 07:55:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727307AbeKIBao (ORCPT + 99 others); Thu, 8 Nov 2018 20:30:44 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:44162 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726700AbeKIBao (ORCPT ); Thu, 8 Nov 2018 20:30:44 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C37D880D; Thu, 8 Nov 2018 07:54:36 -0800 (PST) Received: from [10.1.196.75] (e110467-lin.cambridge.arm.com [10.1.196.75]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 915EA3F5CF; Thu, 8 Nov 2018 07:54:33 -0800 (PST) Subject: Re: [PATCH 13/36] dt-bindings: arm: Convert PMU binding to json-schema To: Rob Herring , Will Deacon , Thomas Petazzoni Cc: Mark Rutland , devicetree@vger.kernel.org, Kumar Gala , Grant Likely , Arnd Bergmann , Tom Rini , Frank Rowand , Linus Walleij , Pantelis Antoniou , "linux-kernel@vger.kernel.org" , Bjorn Andersson , Mark Brown , Geert Uytterhoeven , Jonathan Cameron , Olof Johansson , linuxppc-dev , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" References: <20181005165848.3474-1-robh@kernel.org> <20181005165848.3474-14-robh@kernel.org> <20181009115713.GE6248@arm.com> From: Robin Murphy Message-ID: <08738708-1c38-fab7-eb34-694e5f4d4b7e@arm.com> Date: Thu, 8 Nov 2018 15:54:31 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/11/2018 19:32, Rob Herring wrote: > On Tue, Oct 9, 2018 at 6:57 AM Will Deacon wrote: >> >> Hi Rob, >> >> On Fri, Oct 05, 2018 at 11:58:25AM -0500, Rob Herring wrote: >>> Convert ARM PMU binding to DT schema format using json-schema. >>> >>> Cc: Will Deacon >>> Cc: Mark Rutland >>> Cc: linux-arm-kernel@lists.infradead.org >>> Cc: devicetree@vger.kernel.org >>> Signed-off-by: Rob Herring >>> --- >>> Documentation/devicetree/bindings/arm/pmu.txt | 70 -------------- >>> .../devicetree/bindings/arm/pmu.yaml | 96 +++++++++++++++++++ >>> 2 files changed, 96 insertions(+), 70 deletions(-) >>> delete mode 100644 Documentation/devicetree/bindings/arm/pmu.txt >>> create mode 100644 Documentation/devicetree/bindings/arm/pmu.yaml >> >> [...] >> >>> -- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu >>> - interrupt (PPI) then 1 interrupt should be specified. >> >> [...] >> >>> + interrupts: >>> + oneOf: >>> + - maxItems: 1 >>> + - minItems: 2 >>> + maxItems: 8 >>> + description: 1 interrupt per core. >>> + >>> + interrupts-extended: >>> + $ref: '#/properties/interrupts' >> >> This seems like a semantic different between the two representations, or am >> I missing something here? Specifically, both the introduction of >> interrupts-extended and also dropping any mention of using a single per-cpu >> interrupt (the single combined case is no longer support by Linux; not sure >> if you want to keep it in the binding). > > In regards to no support for the single combined interrupt, it looks > like Marvell Armada SoCs at least (armada-375 is what I'm looking at) > have only a single interrupt. Though the interrupt gets routed to MPIC > which then has a GIC PPI. So it isn't supported or happens to work > still since it is a PPI? Well, the description of the MPIC in the Armada XP functional spec says: "Interrupt sources ID0–ID28 are private events per CPU. Thus, each processor has a different set of events map interrupts ID0–ID28." Odd grammar aside, that would seem to imply that <&mpic 3> is a per-cpu interrupt itself, thus AFAICS so long as it's cascaded to a GIC PPI and not an SPI then there's no issue there. Robin.