Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp153839imu; Thu, 8 Nov 2018 16:47:54 -0800 (PST) X-Google-Smtp-Source: AJdET5eA6W1rd/69Gjd0tckxN7pgdqaFoHbZBp4g2cVWBCSNTVi5/zW+7LHTX7Hx5As+fGGw/LV4 X-Received: by 2002:a17:902:8f8f:: with SMTP id z15-v6mr6774544plo.257.1541724474624; Thu, 08 Nov 2018 16:47:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541724474; cv=none; d=google.com; s=arc-20160816; b=1JoBkxHJhlfir3GSEvxHV+u9Ea2uSFxgoJ+tDOjjn2NjDqkJdRpGQ7lMbhxm8KqYrM THiMTiu2LfwEu2dM/GC7U5/Vz02b4CKL5g5RKjnttsR0PFkEQX03Bly0pqDyLMmCU7eS 3H1qK45Qf3xYxm6qWwncd8qmJ9wN+/ZwTOKWcxpg1l+AL2A78v2v6PKt43QgBRaEy3XU ZsIT+w7TQDoYUzakADzMM5f7vZ+LMFvxbgOc+8s0SfF4+1tLuCr7/0YSgUaC25liMfba ynxhVhcjX3svEJNbJZA+/QafDC/FaRtMbDE3mDdDoZb8X0C0KypZ91vq86l38/hq8QZX 52SQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:dkim-signature; bh=UdhTRWSUVEcWBscAsLhgTjRfmWQlTGz+ikL0XCjUXZA=; b=QBvWO00SE5YkBrsfOHPG3eSkAuGmrxDzc+M1LRFtDVsOo5ZAtoqIrRJHcbN4Mg91in MzNFmCsIQMUetX3LU6ez+AwVEKQCdTUNg8Prxgvv1LOrAc/j5Asj/0zx/AifxeT8ZDM+ K411+Bmj1FhERWJd58Vck/RhquFdAAM5E4554F94gZ+zhmZRZfL1Hpo0apA891aDGODl YX65luagRwxY67z7KPmPjhOmdcYvHYs6+S2CWX9qAe/REcqou2F6qLHIUuhhhAZx4MnS mExki0YwL7SnyEVnpO1y9OQKec5rct/JrRBBi1CahcyBSI1c+OL5xjuFx/E2fxE63l9g hkdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amacapital-net.20150623.gappssmtp.com header.s=20150623 header.b=SQgyPuvl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d76-v6si5223407pfj.124.2018.11.08.16.47.39; Thu, 08 Nov 2018 16:47:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@amacapital-net.20150623.gappssmtp.com header.s=20150623 header.b=SQgyPuvl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727629AbeKIKXs (ORCPT + 99 others); Fri, 9 Nov 2018 05:23:48 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:42947 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727560AbeKIKXs (ORCPT ); Fri, 9 Nov 2018 05:23:48 -0500 Received: by mail-wr1-f68.google.com with SMTP id y15-v6so125626wru.9 for ; Thu, 08 Nov 2018 16:45:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amacapital-net.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=UdhTRWSUVEcWBscAsLhgTjRfmWQlTGz+ikL0XCjUXZA=; b=SQgyPuvlFn/v52UaPq733+x1QveHknP5PUo2HaPfIecqcPf+VPCamW3qR4YBLxdR6Z ykFO57bwa5kLPlH8rFYOT4Pz+ABEcmzQGmK2ZDjNXSJmMCDIFHEhmnFP7tqvY202S1UK AYCfX7DIBXRSytZjK71k6yMBc8r3RqwJwZ12E53Hjq4SCQbQ5WnsAdkF5vBXO9NcrE+t ktODzQ4IAIHABS1CJvoEoSeRkWCjalwK4mg84eOWIzdmKzvqDWMLZPvKSRXHBMxkWBm5 gEtDFyEed9LbjcZZqhPwq1QKVCTfPq3b+1E6ClsdUg3tTiO3keHgbUTMaU9RPIrZgxMY sd9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=UdhTRWSUVEcWBscAsLhgTjRfmWQlTGz+ikL0XCjUXZA=; b=joAcDE63DB5eHGd7qDSFmBmWvcGsmxvjt2NgEy0zPFhWYmwZCZBPT7MgqnsRyHp+Zr pLjsfxaofHSXVM/+nfDCwFdkENyxEFeRxKdv9YlKJZqGhriyT9cAB4ZxD2LijZZd6hfU CuvYNJayovj3UgPEC5fSwMnThjT0vTrPUpOPpLb4KlSfkBY8bDJozfmyl1ywShrBw+up TSJQfCgRHyOBKv4i/1qLotBQaGzALfd3TyCHqfLaXhEMCtCe7/9p//y3neS57Y+rR/61 m1MXCZxFMkpC+nyNK1zgdwsyVkv4A2ayMnKOTLD9CCUcQXwF3757lbU2SRKk+d+MUN/M jUTA== X-Gm-Message-State: AGRZ1gKXTsnZdV+E8aJ+mWnV9ytDJV4F9uIGM1FIgsia5GDCgTw+JFzs pqz3mNCMwnJnUkM6QbxGaqlzgiPH17ghZT+8EcqBqg== X-Received: by 2002:a5d:4450:: with SMTP id x16-v6mr5986222wrr.308.1541724338245; Thu, 08 Nov 2018 16:45:38 -0800 (PST) MIME-Version: 1.0 References: <20181011151523.27101-1-yu-cheng.yu@intel.com> <20181011151523.27101-5-yu-cheng.yu@intel.com> <4295b8f786c10c469870a6d9725749ce75dcdaa2.camel@intel.com> <043a17ef-dc9f-56d2-5fba-1a58b7b0fd4d@intel.com> <20181108220054.GP3074@bombadil.infradead.org> <20181109003225.GQ3074@bombadil.infradead.org> In-Reply-To: <20181109003225.GQ3074@bombadil.infradead.org> From: Andy Lutomirski Date: Thu, 8 Nov 2018 16:45:26 -0800 Message-ID: Subject: Re: [PATCH v5 04/27] x86/fpu/xstate: Add XSAVES system states for shadow stack To: Matthew Wilcox Cc: Dave Hansen , Yu-cheng Yu , X86 ML , "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , LKML , "open list:DOCUMENTATION" , Linux-MM , linux-arch , Linux API , Arnd Bergmann , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H. J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V. Shankar" , "Shanbhogue, Vedvyas" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 8, 2018 at 4:32 PM Matthew Wilcox wrote: > > On Thu, Nov 08, 2018 at 03:35:02PM -0800, Dave Hansen wrote: > > On 11/8/18 2:00 PM, Matthew Wilcox wrote: > > > struct a { > > > char c; > > > struct b b; > > > }; > > > > > > we want struct b to start at offset 8, but with __packed, it will start > > > at offset 1. > > > > You're talking about how we want the struct laid out in memory if we > > have control over the layout. I'm talking about what happens if > > something *else* tells us the layout, like a hardware specification > > which is what is in play with the XSAVE instruction dictated layout > > that's in question here. > > > > What I'm concerned about is a structure like this: > > > > struct foo { > > u32 i1; > > u64 i2; > > }; > > > > If we leave that to natural alignment, we end up with a 16-byte > > structure laid out like this: > > > > 0-3 i1 > > 3-8 alignment gap > > 8-15 i2 > > I know you actually meant: > > 0-3 i1 > 4-7 pad > 8-15 i2 > > > Which isn't what we want. We want a 12-byte structure, laid out like this: > > > > 0-3 i1 > > 4-11 i2 > > > > Which we get with: > > > > struct foo { > > u32 i1; > > u64 i2; > > } __packed; > > But we _also_ get pessimised accesses to i1 and i2. Because gcc can't > rely on struct foo being aligned to a 4 or even 8 byte boundary (it > might be embedded in "struct a" from above). > In the event we end up with a hardware structure that has not-really-aligned elements, I suspect we can ask gcc for a new extension to help. Or maybe some hack like: struct foo { u32 i1; struct { u64 i2; } __attribute__((packed)); }; would do the trick.