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References: <20181025055833.28471-1-ganapatrao.kulkarni@cavium.com>
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From:   Ganapatrao Kulkarni <gklkml16@gmail.com>
Date:   Fri, 9 Nov 2018 15:51:15 +0530
Message-ID: <CAKTKpr5mtSuRLfaGe+nQOsEYSP7MghsxhjtVgKmR=jAnrAn1Kg@mail.gmail.com>
Subject: Re: [PATCH v7 2/2] ThunderX2, perf : Add Cavium ThunderX2 SoC UNCORE
 PMU driver
To:     Randy Dunlap <rdunlap@infradead.org>
Cc:     Ganapatrao Kulkarni <Ganapatrao.Kulkarni@cavium.com>,
        linux-doc@vger.kernel.org, LKML <linux-kernel@vger.kernel.org>,
        linux-arm-kernel@lists.infradead.org,
        Will Deacon <Will.Deacon@arm.com>,
        Mark Rutland <mark.rutland@arm.com>, suzuki.poulose@arm.com,
        "Nair, Jayachandran" <Jayachandran.Nair@cavium.com>,
        Robert Richter <Robert.Richter@cavium.com>,
        Vadim.Lomovtsev@cavium.com, Jan.Glauber@cavium.com
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Sender: linux-kernel-owner@vger.kernel.org
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On Thu, Oct 25, 2018 at 9:42 PM Randy Dunlap <rdunlap@infradead.org> wrote:
>
> On 10/24/18 10:59 PM, Kulkarni, Ganapatrao wrote:
> > diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
> > index 08ebaf7cca8b..c1956b1af2bb 100644
> > --- a/drivers/perf/Kconfig
> > +++ b/drivers/perf/Kconfig
> > @@ -87,6 +87,15 @@ config QCOM_L3_PMU
> >          Adds the L3 cache PMU into the perf events subsystem for
> >          monitoring L3 cache events.
> >
> > +config THUNDERX2_PMU
> > +        tristate "Cavium ThunderX2 SoC PMU UNCORE"
> > +     depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA
> > +        default m
> > +     help
> > +       Provides support for ThunderX2 UNCORE events.
> > +       The SoC has PMU support in its L3 cache controller (L3C) and
> > +       in the DDR4 Memory Controller (DMC).
> > +
> >  config XGENE_PMU
> >          depends on ARCH_XGENE
> >          bool "APM X-Gene SoC PMU"
>
> Please fix the Kconfig indentation.  Use one tab (not spaces) for each of
> tristate, depends, default, and help.  (yes, some of them are tabs and some
> are spaces.)

thanks, i will update.
>
>
> --
> ~Randy

thanks
Ganapat