Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp3329838imu; Sun, 11 Nov 2018 12:30:49 -0800 (PST) X-Google-Smtp-Source: AJdET5ePz5RyU8CRU8VXgq0uD6Wtg7wPsmxZDvX197D8aRQV1IxqCGOk9N99ORC+w7LPn/IBEOQo X-Received: by 2002:a17:902:144:: with SMTP id 62-v6mr16891077plb.142.1541968249747; Sun, 11 Nov 2018 12:30:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541968249; cv=none; d=google.com; s=arc-20160816; b=n2aQyG71c9qcUDAGRguaPmBgTD4ZVdZwFjXliktWzksuiGgKnXAH8Cnzq/12naZIwB pI7T6eCllGyZGef1bDmNpXo5cIxkqdg/HYhDjOJOfbjeOi7JEChjzgssifX4xCQf0WIq LsQ4WR7M00+OrLNtZAt3vk4GyEGyizaKqY4I1C+BluTqpZSqVm+OaMWRBytairATyBns Xf7m97b5Qeci/NzVR0p1Me8k9QqX0yIx2qyCBo9T4TjjXeG18vGpIeDK5k5L/saDL9wz 6s0DcWmjs8XX5RQ5uVILIm2PX1RR4UZXgmCSJ2L+umMX0BF09p8fYJKCmf1smoIY4W9q SV8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:in-reply-to:subject:message-id:date:cc:to :from:mime-version:content-transfer-encoding:content-disposition; bh=8AggzrKq07ed/1HCBdfa8FqGh5y13BtNE37mWbvNbTE=; b=FDctssvK34PBvNp90dg2QSbjyYwTOTeorTbaNvQPLU9prUjz8WwCS5CeMiSEnrWk2e MV9mGQzqov/0BaoqkymrHSr38Yjh74IqlUGsznvr3g2lVEP6v/rhVnUse7y2d6KCq0NC 9z9I6VUGE1iUbOinuDHlXy8i6p6xrgxOzBXhkJnjmL4DC8xhh1V9tv4uKXRyqfvMtQT+ AyML4Z6YXdZ3dttT+RPxTUgDRu7STb2CWLe6rYoWq4DO76DM8HyGLcYjLsB73Ce3jZBg PY8lbQvKwyonm2DqzpeAOW/TC4qpyUj6KWEd091aP1r/G3Kn5kuy0G7NeiXhQ/VXyPdT Q8sA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o125-v6si14114549pgo.302.2018.11.11.12.30.34; Sun, 11 Nov 2018 12:30:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731509AbeKLGTg (ORCPT + 99 others); Mon, 12 Nov 2018 01:19:36 -0500 Received: from shadbolt.e.decadent.org.uk ([88.96.1.126]:50502 "EHLO shadbolt.e.decadent.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730434AbeKLFsV (ORCPT ); Mon, 12 Nov 2018 00:48:21 -0500 Received: from [192.168.4.242] (helo=deadeye) by shadbolt.decadent.org.uk with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1gLvsh-0000oF-La; Sun, 11 Nov 2018 19:58:51 +0000 Received: from ben by deadeye with local (Exim 4.91) (envelope-from ) id 1gLvsa-0001rZ-9N; Sun, 11 Nov 2018 19:58:44 +0000 Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit MIME-Version: 1.0 From: Ben Hutchings To: linux-kernel@vger.kernel.org, stable@vger.kernel.org CC: akpm@linux-foundation.org, "Markos Chandras" Date: Sun, 11 Nov 2018 19:49:05 +0000 Message-ID: X-Mailer: LinuxStableQueue (scripts by bwh) Subject: [PATCH 3.16 341/366] MIPS: asm: compiler: Add new macros to set ISA and arch asm annotations In-Reply-To: X-SA-Exim-Connect-IP: 192.168.4.242 X-SA-Exim-Mail-From: ben@decadent.org.uk X-SA-Exim-Scanned: No (on shadbolt.decadent.org.uk); SAEximRunCond expanded to false Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 3.16.61-rc1 review patch. If anyone has any objections, please let me know. ------------------ From: Markos Chandras commit be5136988e25ae0dc8379fcb937efc63d87aba9e upstream. There are certain places where the code uses .set mips32 or .set mips64 or .set arch=r4000. In preparation of MIPS R6 support, and in order to use as less #ifdefs as possible, we define new macros to set similar annotations for MIPS R6. Signed-off-by: Markos Chandras [bwh: Backported to 3.16: We don't support MIPS R6 but I have applied a commit that uses MIPS_ISA_LEVEL_RAW. Add the R2 definitions only.] Signed-off-by: Ben Hutchings --- arch/mips/include/asm/compiler.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) --- a/arch/mips/include/asm/compiler.h +++ b/arch/mips/include/asm/compiler.h @@ -16,4 +16,10 @@ #define GCC_REG_ACCUM "accum" #endif +/* MIPS64 is a superset of MIPS32 */ +#define MIPS_ISA_LEVEL "mips64r2" +#define MIPS_ISA_ARCH_LEVEL "arch=r4000" +#define MIPS_ISA_LEVEL_RAW mips64r2 +#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW + #endif /* _ASM_COMPILER_H */