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[209.132.180.67]) by mx.google.com with ESMTP id 37si14901005pgw.590.2018.11.11.20.27.37; Sun, 11 Nov 2018 20:27:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@brainfault-org.20150623.gappssmtp.com header.s=20150623 header.b=QRriG82f; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730722AbeKLOSf (ORCPT + 99 others); Mon, 12 Nov 2018 09:18:35 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:53819 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730558AbeKLOSf (ORCPT ); Mon, 12 Nov 2018 09:18:35 -0500 Received: by mail-wm1-f68.google.com with SMTP id f10-v6so7041540wme.3 for ; Sun, 11 Nov 2018 20:27:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=/sS9qOFTYQqdHnYlhyaiAgHwrmTJ+8DMJ1q1QxhUg5U=; b=QRriG82frU04AGrJaiFSzp+hEk19z0jPwwCzfmI8CQRiR3V7S5SAAehM15bJTJvIJv GQ+78OZAcasGnt2qonN20tjzJT8X+ZcuPoFDzrfiDmaVRJHGPFohd6NR/v4GNTAPqjrl mxz0khZV3JMCnDseVM6rBRMGHpS/U7cmbiLsmKW7EoKTby6lPdhdZHsxTInhERBJ0XTS g9uJl/go4UQXZB8GUJ7+62ObZUPv+6C51bSSi2D2KeOX6Co/z/mEwJKHZ9aJ6RtRLMf1 CShlvTDLxiqVcablIHWzmQmyb8Xfxsz3Ze9J3ZQ6e4suYsGX6UCWwHgOwWh7QncPLl7C /ECQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=/sS9qOFTYQqdHnYlhyaiAgHwrmTJ+8DMJ1q1QxhUg5U=; b=iJkQcqgag+SeORyD2EIsk0tFRcc8HHv0LPeppbgElDhgUpEfGsIDmMgG3TjSSNZ27R xnfALRQ2CgtQqXS0BZC0Ars2pE2vh32+aaFMWP/HxZAOnkntG3/yxtWF+SSGsA/+ldKt q5mgmZ6svC4UxoNR0u/4ty8pZIa7qQaOp4pZ/csKFPor4qeAltrnzZtxzyVuBOaoD8GS yVdYivu8wWjLOtROVbAUbH+VFJsLEQ21k9JfgQQNigmiQmdSlvX4phfUSBT+qM/wxeAg Q6nys41c0rT2besHYZl36y0TDVxKPijXOv3UodGS+BPPhu+OxKtDMRvYVyTpBaWsCnxh P6vw== X-Gm-Message-State: AGRZ1gKlfw4iNc5fe5AZSBx/fFjH8kQ9GR2BaQ4LYfrDOHLMtd9ZT10f aDs+gHbgINVl70UkuO0EIXorckfHFg8ug1MB0kR7Rg== X-Received: by 2002:a1c:d785:: with SMTP id o127-v6mr445176wmg.56.1541996831267; Sun, 11 Nov 2018 20:27:11 -0800 (PST) MIME-Version: 1.0 References: <20181022114517.22748-1-anup@brainfault.org> <20181022114517.22748-2-anup@brainfault.org> <20181109084256.GA6508@infradead.org> In-Reply-To: <20181109084256.GA6508@infradead.org> From: Anup Patel Date: Mon, 12 Nov 2018 09:57:02 +0530 Message-ID: Subject: Re: [PATCH 1/4] irqchip: sifive-plic: Pre-compute context hart base and enable base To: Christoph Hellwig Cc: Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Jason Cooper , Marc Zyngier , Atish Patra , linux-riscv@lists.infradead.org, "linux-kernel@vger.kernel.org List" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Nov 9, 2018 at 2:12 PM Christoph Hellwig wrote: > > On Mon, Oct 22, 2018 at 05:15:14PM +0530, Anup Patel wrote: > > This patch does following optimizations: > > 1. Pre-compute hart base for each context handler > > 2. Pre-compute enable base for each context handler > > Why? This is micro-optimizations. We don't need to re-compute hart base and hart enable base everytime. > > > 3. Have enable lock for each context handler instead > > of global plic_toggle_lock > > Why? Also even if you want this it should be a separate patch. Well, the PLIC register space it a bit strange. Most PLIC context specific registers are in one place except context IRQ enable registers which are part of global registers. To handle this, we had a global plic_toggle_lock which was taken whenever PLIC driver touched context IRQ enable registers. Instead of this, we can have per-context IRQ enable lock for more granular locking. Later when we implement IRQ set_affinity, we touch IRQ enable registers of each context whenever IRQ affinity changes. This fine grained IRQ enable locking helps when IRQ load-balancer is changing affinity of different IRQs parallely on separate cores. Again this is a micro-optimization. > > > #define PRIORITY_BASE 0 > > -#define PRIORITY_PER_ID 4 > > +#define PRIORITY_PER_ID 4 > > Also please drop the random whitespace changes. Instead of dropping I will make it separate patch because we are replacing "\t" between #define and define_name with a space. Regards, Anup