Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp3982679imu; Mon, 12 Nov 2018 03:59:18 -0800 (PST) X-Google-Smtp-Source: AJdET5d7xyQdlcjUdIdxlbaanusODoJuEVW2CcMqakBox9EzfpNUxlG73k0CSoFQvsizmS//i8h4 X-Received: by 2002:a17:902:aa8d:: with SMTP id d13-v6mr684463plr.74.1542023958610; Mon, 12 Nov 2018 03:59:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542023945; cv=none; d=google.com; s=arc-20160816; b=DeK8DW5aTAw9Qx8Xz/AU35iW4QWeLY+qtsbWDirpa1WjUmK/cprg2TCXFrNi432/25 ytLRyhviPAvkz+bxCg0q0J2VEln+N0KdQnPJDPbIDGoi6otl2w4l6fahC3YNjDMUxIuW YBeB1swGYKg6zrTLkYlC+SOYnXWWrjHUtfMgDXti37ZVufTYcHeQMUhMLeSUz8F81jQX jnBCG/RmwALjv2j1Hqa0HZtYPogogcoiJz5x+pu3nTBS2NeSO/wvcRBkHGAdN0zgPtJ2 czMFs8A9FLA1q6LhEjsG0USfLqsjWYq8Q7jrlnRvJ+94AN9NsUMxtApHpexlmFu2udXJ 2Ujg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=Cy91B4YVPd9iNgkY2MAVhJr3ZyYCLZZWNCjy3wS3LJQ=; b=0XqRqP5B3bWbf8p8HlsgkvoAx1O+5AxeQNgPkaX2oiXNQjKWcURwNi5lnFKfOF0J27 1FGXfGjYptm3v4fsvnefP5C3jHwvid9L50k6kf+rOYnC6jtjtpN82hjk7XURXZnckzaY wOQqX2xfyLtXmEl+EsVo+9+3ufGK2QJpAO0tViYEavtTiHRZtW0Yf4JUHrH2ogVFMQKr oZcJpRmCHmbzfY6Vi4XyzJLV/nM5sZleouwXuGmTE5bYew94AoDKCfy7GkuGQMPHj48j TPy4A/0oKgeCKPtPNfNJ1P3LBe431QHNJGU4Lum6dCuj5CqPMtNORcJuuls+zt8VA/3+ CR+w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i2si16189042pgl.153.2018.11.12.03.58.50; Mon, 12 Nov 2018 03:59:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730162AbeKLVvR (ORCPT + 99 others); Mon, 12 Nov 2018 16:51:17 -0500 Received: from foss.arm.com ([217.140.101.70]:34840 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729246AbeKLVvQ (ORCPT ); Mon, 12 Nov 2018 16:51:16 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 208AF1682; Mon, 12 Nov 2018 03:58:20 -0800 (PST) Received: from e112298-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 545253F5A0; Mon, 12 Nov 2018 03:58:18 -0800 (PST) From: Julien Thierry To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Julien Thierry Subject: [PATCH v6 24/24] arm64: Enable the support of pseudo-NMIs Date: Mon, 12 Nov 2018 11:57:15 +0000 Message-Id: <1542023835-21446-25-git-send-email-julien.thierry@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542023835-21446-1-git-send-email-julien.thierry@arm.com> References: <1542023835-21446-1-git-send-email-julien.thierry@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a build option and a command line parameter to build and enable the support of pseudo-NMIs. Signed-off-by: Julien Thierry Suggested-by: Daniel Thompson Cc: Catalin Marinas Cc: Will Deacon --- Documentation/admin-guide/kernel-parameters.txt | 6 ++++++ arch/arm64/Kconfig | 14 ++++++++++++++ arch/arm64/kernel/cpufeature.c | 11 ++++++++++- 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 81d1d5a..63dbd56 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1183,6 +1183,12 @@ to discrete, to make X server driver able to add WB entry later. This parameter enables that. + enable_pseudo_nmi [ARM64] + Enables support for pseudo-NMIs in the kernel. This + requires both the kernel to be built with + CONFIG_ARM64_PSEUDO_NMI and to be running on a + platform with GICv3. + enable_timer_pin_1 [X86] Enable PIN 1 of APIC timer Can be useful to work around chipset bugs diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 787d785..4729cf0 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -958,6 +958,20 @@ config ARM64_SSBD If unsure, say Y. +config ARM64_PSEUDO_NMI + bool "Support for NMI-like interrupts" + select CONFIG_ARM_GIC_V3 + help + Adds support for mimicking Non-Maskable Interrupts through the use of + GIC interrupt priority. This support requires version 3 or later of + Arm GIC. + + This high priority configuration for interrupts need to be + explicitly enabled through the new kernel parameter + "enable_pseudo_nmi". + + If unsure, say N + menuconfig ARMV8_DEPRECATED bool "Emulate deprecated/obsolete ARMv8 instructions" depends on COMPAT diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 58a4978..acf1d06 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1149,10 +1149,19 @@ static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) #endif /* CONFIG_ARM64_RAS_EXTN */ #ifdef CONFIG_ARM64_PSEUDO_NMI +static bool enable_pseudo_nmi; + +static int __init early_enable_pseudo_nmi(char *p) +{ + enable_pseudo_nmi = true; + return 0; +} +early_param("enable_pseudo_nmi", early_enable_pseudo_nmi); + static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, int scope) { - return false; + return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); } #endif -- 1.9.1