Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp3985886imu; Mon, 12 Nov 2018 04:02:10 -0800 (PST) X-Google-Smtp-Source: AJdET5dFjdNKCCnMCTucAzsFw1/J1k0OwaLivcp5XnPUZWYxFsnTtL6TWq+VvkkRJEg96FrKUv8w X-Received: by 2002:a17:902:680f:: with SMTP id h15mr686214plk.40.1542024130635; Mon, 12 Nov 2018 04:02:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542024130; cv=none; d=google.com; s=arc-20160816; b=bgEbox2iLgvnU7jtT3y13wTZFyHNKyx6e1j1q83CaICuiCrZ+PMzaJP7cifvui2muZ QZOowDBMrCeKGqMtPovQiLY+KYLUsTAgwB7HunJFzktNQp4Qo5Ph0dLNPPSuGTM7Kd6r H7sQq58iwMPJ4Jb0wL982h65Ykn47ZDk5lfB5kclWkWcpENTsBz9jR0O9rIuLHk9LuMh N9g8pFUpZER+gDzLc1xhPh3xh7CFl8qR+dP1vQoFgAzvi4ZPBtF3nte/wIalLu6J9Dr7 pFFTGdKSc9xYmBR1gqLOF4QTkCq1rs54u/IDXIFOk2NKCdYQRvnWxRoMmrk9Oh5YZoOu JJkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=5roYOq0DloQmIgjs/cIhmsOpbbcqS1/HJncg35XSldQ=; b=WoKaSGyxfJZP2b6UwVnyKcRj3MBR6qCBzEU4lpRCAK6UzVqFGmwOG4tPJPuoJsdhhA s+C5yWAettNKGQSFVodX8tPmggxsr8+UlLVyrNP05O899MplfWRteHIwfpgqa3NXgHkG NSQQNHbbR4lgyM7vuZbz/BPtu5lNcg2mdMiLlXZ4zEJxe49QcCmaldr1SdEAULlk98H8 2yDp9wrZ8yH+bd8tXBuu3zhkClcL796bOjiGpYFCgnguVeuYUFHzgkvprscud6k5MfPL Z+mobNTtRthLozUTKRTdy/lwocLS5QsPkFPVOg32nUf74L3700j+lniHnm7HPW47u9sW 3mJQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bj7-v6si17449404plb.193.2018.11.12.04.01.48; Mon, 12 Nov 2018 04:02:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729705AbeKLVuh (ORCPT + 99 others); Mon, 12 Nov 2018 16:50:37 -0500 Received: from foss.arm.com ([217.140.101.70]:34562 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729645AbeKLVuh (ORCPT ); Mon, 12 Nov 2018 16:50:37 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CF2EE1688; Mon, 12 Nov 2018 03:57:40 -0800 (PST) Received: from e112298-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D64DD3F5A0; Mon, 12 Nov 2018 03:57:38 -0800 (PST) From: Julien Thierry To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Julien Thierry , Oleg Nesterov Subject: [PATCH v6 06/24] arm64: ptrace: Provide definitions for PMR values Date: Mon, 12 Nov 2018 11:56:57 +0000 Message-Id: <1542023835-21446-7-git-send-email-julien.thierry@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542023835-21446-1-git-send-email-julien.thierry@arm.com> References: <1542023835-21446-1-git-send-email-julien.thierry@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce fixed values for PMR that are going to be used to mask and unmask interrupts by priority. These values are chosent in such a way that a single bit (GIC_PMR_UNMASKED_BIT) encodes the information whether interrupts are masked or not. Signed-off-by: Julien Thierry Suggested-by: Daniel Thompson Cc: Oleg Nesterov Cc: Catalin Marinas Cc: Will Deacon --- arch/arm64/include/asm/ptrace.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index fce22c4..ce6998c 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -25,6 +25,12 @@ #define CurrentEL_EL1 (1 << 2) #define CurrentEL_EL2 (2 << 2) +/* PMR values used to mask/unmask interrupts */ +#define GIC_PRIO_IRQON 0xf0 +#define GIC_PRIO_STATUS_SHIFT 6 +#define GIC_PRIO_STATUS_BIT (1 << GIC_PRIO_STATUS_SHIFT) +#define GIC_PRIO_IRQOFF (GIC_PRIO_IRQON ^ GIC_PRIO_STATUS_BIT) + /* Additional SPSR bits not exposed in the UABI */ #define PSR_IL_BIT (1 << 20) -- 1.9.1