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[209.132.180.67]) by mx.google.com with ESMTP id h68-v6si22334956pfb.142.2018.11.13.02.00.39; Tue, 13 Nov 2018 02:00:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732053AbeKMTzy (ORCPT + 99 others); Tue, 13 Nov 2018 14:55:54 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:54444 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731616AbeKMTzy (ORCPT ); Tue, 13 Nov 2018 14:55:54 -0500 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id wAD9rjS8028424; Tue, 13 Nov 2018 10:58:08 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2nnq3j8qu8-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 13 Nov 2018 10:58:08 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 990DF31; Tue, 13 Nov 2018 09:58:07 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6D8742715; Tue, 13 Nov 2018 09:58:07 +0000 (GMT) Received: from [10.201.21.58] (10.75.127.45) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 13 Nov 2018 10:58:06 +0100 Subject: Re: [PATCH 3/3] ARM: dts: stm32: Add hwlock for pinctrl To: Benjamin Gaignard , , CC: , , , , , Benjamin Gaignard References: <20181113095142.32015-1-benjamin.gaignard@st.com> <20181113095142.32015-4-benjamin.gaignard@st.com> From: Alexandre Torgue Message-ID: <2e76818f-28a0-1151-11f0-a9e8d3b5fd09@st.com> Date: Tue, 13 Nov 2018 10:58:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <20181113095142.32015-4-benjamin.gaignard@st.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG5NODE3.st.com (10.75.127.15) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-11-13_06:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Benjamin On 11/13/18 10:51 AM, Benjamin Gaignard wrote: > Define a hwspinlock to be used by pin-controller > > Signed-off-by: Benjamin Gaignard > --- > arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 1 + > 1 file changed, 1 insertion(+) > In commit title please add for which SoC it is targeted. If you don't have to send new version for driver or dt-bindings, I will do it when I'll apply. regards Alex > diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi > index c4851271e810..2886e5a6ac27 100644 > --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi > +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi > @@ -14,6 +14,7 @@ > ranges = <0 0x50002000 0xa400>; > interrupt-parent = <&exti>; > st,syscfg = <&exti 0x60 0xff>; > + hwlocks = <&hsem 0>; > pins-are-numbered; > > gpioa: gpio@50002000 { >