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[209.132.180.67]) by mx.google.com with ESMTP id m187-v6si23221075pfm.159.2018.11.13.05.10.53; Tue, 13 Nov 2018 05:11:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387476AbeKMXHX (ORCPT + 99 others); Tue, 13 Nov 2018 18:07:23 -0500 Received: from relmlor4.renesas.com ([210.160.252.174]:13707 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1732728AbeKMXHX (ORCPT ); Tue, 13 Nov 2018 18:07:23 -0500 Received: from unknown (HELO relmlir3.idc.renesas.com) ([10.200.68.153]) by relmlie3.idc.renesas.com with ESMTP; 13 Nov 2018 22:09:16 +0900 Received: from relmlii2.idc.renesas.com (relmlii2.idc.renesas.com [10.200.68.66]) by relmlir3.idc.renesas.com (Postfix) with ESMTP id E37DAB754D; Tue, 13 Nov 2018 22:09:16 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.54,499,1534777200"; d="scan'208";a="297422157" Received: from unknown (HELO vbox.ree.adwin.renesas.com) ([10.226.37.67]) by relmlii2.idc.renesas.com with ESMTP; 13 Nov 2018 22:09:14 +0900 From: Phil Edworthy To: Marc Zyngier , Thomas Gleixner , Jason Cooper , Rob Herring , Mark Rutland Cc: Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Phil Edworthy , devicetree@vger.kernel.org Subject: [PATCH v3 0/2] irqchip: Add support for Renesas RZ/N1 GPIO interrupt multiplexer Date: Tue, 13 Nov 2018 13:09:08 +0000 Message-Id: <20181113130910.22130-1-phil.edworthy@renesas.com> X-Mailer: git-send-email 2.17.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On RZ/N1 devices, there are lots of GPIO interrupts that are multiplexed before getting to the GIC interrupt controller. Other than the multiplexing, there is no other logic applied to the signals. The multiplexing cannot be handled dynamically because there is another CPU that runs firmware. It's likely that the firmware will use some of these GPIO interrupts and so we don't want them to move around. Signed-off-by: Phil Edworthy --- v3: - Use 'interrupt-map' DT property to map the interrupts, this is very similar to PCIe MSI. The only difference is that we need to get hold of the interrupt specifier for the interupts coming into the irqmux. I had completely messed up the use of 'interrupt-map' in v2... oops. - Do not use a chained interrupt controller. v2: - Split DT bindings into separate patch. - Use interrupt-map to allow the GPIO controller info to be specified as part of the irq. - Don't show status in binding examples. - Don't show the soc/board split in binding doc. - Renamed struct and funcs from 'girq' to a more comprehenisble 'irqmux'. Phil Edworthy (2): dt-bindings/interrupt-controller: rzn1: Add RZ/N1 gpio irq mux binding irqchip: Add support for Renesas RZ/N1 GPIO interrupt multiplexer .../interrupt-controller/renesas,rzn1-mux.txt | 73 +++++++ drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/rzn1-irq-mux.c | 205 ++++++++++++++++++ 4 files changed, 288 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzn1-mux.txt create mode 100644 drivers/irqchip/rzn1-irq-mux.c -- 2.17.1