Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S264353AbUAIUCn (ORCPT ); Fri, 9 Jan 2004 15:02:43 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S264246AbUAIUCn (ORCPT ); Fri, 9 Jan 2004 15:02:43 -0500 Received: from colo.lackof.org ([198.49.126.79]:50336 "EHLO colo.lackof.org") by vger.kernel.org with ESMTP id S264353AbUAIUC2 (ORCPT ); Fri, 9 Jan 2004 15:02:28 -0500 Date: Fri, 9 Jan 2004 13:02:23 -0700 From: Grant Grundler To: Jeremy Higdon Cc: Grant Grundler , Jesse Barnes , linux-kernel@vger.kernel.org, linux-pci@atrey.karlin.mff.cuni.cz, James.Bottomley@steeleye.com Subject: Re: [RFC] Relaxed PIO read vs. DMA write ordering Message-ID: <20040109200223.GA14165@colo.lackof.org> References: <20040107175801.GA4642@sgi.com> <20040107190206.GK17182@parcelfarce.linux.theplanet.co.uk> <20040107222142.GB14951@colo.lackof.org> <20040107230712.GB6837@sgi.com> <20040108063829.GC22317@colo.lackof.org> <20040108173655.GA11168@sgi.com> <20040108184406.GA29210@colo.lackof.org> <20040109071347.GB343099@sgi.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20040109071347.GB343099@sgi.com> User-Agent: Mutt/1.3.28i X-Home-Page: http://www.parisc-linux.org/ Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1655 Lines: 37 On Thu, Jan 08, 2004 at 11:13:47PM -0800, Jeremy Higdon wrote: > What if the host/bridge sets the RO bit on a PIO read? That would > allow a PIO read response to bypass a DMA write. *Any* bridge that is on the common path from CPU/Mem to PCI-X can choose to implement RO anyway it likes. Even though such a bridge may not use PCI-X, the entire system must honor the semantics required by PCI/PCI-X one way or another. RO is optional IMHO. > Now, maybe that > doesn't make much sense with respect to PCI-X. I think it's possible, > though. Or can the RO bit only be set by a device? The ordering of transaction on the way to the device is not the obvious problem here. It's the ordering of transactions originated by the device. A read return is generated by the device on PCI-X since PCI-X supports split transactions. > In any case, if we can do a PIO read to one address space that flushes > DMA ahead of it or another address space that does not, then you would > need a separate version of readX, rather than an extra call to sync > after the read. That would be optimal yes. But a functional pci_sync_consistent() implementation would consist of a MMIO Read using the address space that enforces ordering. As I pointed out earlier, the spec clearly states it's up to the device to specify the ordering, not the device driver. The device driver can only choose to enable the feature or not. grant - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/