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From:   <Alex_Gagniuc@Dellteam.com>
To:     <keith.busch@intel.com>
Subject: Re: [PATCH v2] PCI/MSI: Don't touch MSI bits when the PCI device is
 disconnected
Thread-Topic: [PATCH v2] PCI/MSI: Don't touch MSI bits when the PCI device is
 disconnected
Thread-Index: AQHUT50UQ290XPGvJEGnaSTTjbCF+g==
Date:   Wed, 14 Nov 2018 00:31:13 +0000
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On 11/13/2018 04:56 PM, Keith Busch wrote:=0A=
> On Tue, Nov 13, 2018 at 10:39:15PM +0000, Alex_Gagniuc@Dellteam.com wrote=
:=0A=
>> On 11/12/2018 11:02 PM, Bjorn Helgaas wrote:=0A=
>>> The whole issue of firmware-first, the mechanism by which firmware=0A=
>>> gets control, the System Error enables in Root Port Root Control=0A=
>>> registers, etc., is very murky to me.  Jon has a sort of similar issue=
=0A=
>>> with VMD where he needs to leave System Errors enabled instead of=0A=
>>> disabling them as we currently do.=0A=
>>=0A=
>> Well, OS gets control via _OSC method, and based on that it should=0A=
>> touch/not touch the AER bits. The bits that get set/cleared come from=0A=
>> _HPX method, and there's a more about the FFS described in ACPI spec. It=
=0A=
>> seems that if platform, wants to enable VMD, it should pass the correct=
=0A=
>> bits via _HPX. I'm curious to know in what new twisted way FFS doesn't=
=0A=
>> work as intended.=0A=
> =0A=
> When VMD is enabled, the platform sees a VMD endpoint. It doesn't see=0A=
> any of the root ports on that domain, so ACPI can't provide policies for=
=0A=
> them nor AER registers for the platform to consider controlling.=0A=
=0A=
I'm not understanding the interdependency between RP AER settings and =0A=
VMD. My understanding of VMD is quite rudimentary though, so I'll take =0A=
your word for it.=0A=
=0A=
Alex=0A=
=0A=