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[81.165.188.49]) by smtp.gmail.com with ESMTPSA id c30sm1421696edc.70.2018.11.14.06.37.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 14 Nov 2018 06:37:26 -0800 (PST) Received: from peko by dell.be.48ers.dk with local (Exim 4.89) (envelope-from ) id 1gMwIH-0004kd-6A; Wed, 14 Nov 2018 15:37:25 +0100 From: Peter Korsgaard To: Jerome Brunet Cc: Kevin Hilman , Carlo Caione , Neil Armstrong , linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH RESEND 2/2] arm64: dts: meson: add libretech aml-s805x-ac board References: <20181114101925.10526-3-jbrunet@baylibre.com> <20181114103855.14571-1-jbrunet@baylibre.com> Date: Wed, 14 Nov 2018 15:37:25 +0100 In-Reply-To: <20181114103855.14571-1-jbrunet@baylibre.com> (Jerome Brunet's message of "Wed, 14 Nov 2018 11:38:55 +0100") Message-ID: <87a7mbvi6y.fsf@dell.be.48ers.dk> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.5 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >>>>> "Jerome" == Jerome Brunet writes: > From: Neil Armstrong > Add Libretech aml-s805x-ac board (aka 'La Frite') support > Signed-off-by: Neil Armstrong > Signed-off-by: Jerome Brunet > --- .. > +#include "meson-gxl-s905x.dtsi" > + > +/ { > + compatible = "libretech,aml-s805x-ac", "amlogic,s805x", > + "amlogic,meson-gxl"; > + model = "Libre Computer Board AML-S805X-AC"; No mention of 'La Frite'? > + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x0 0x0 0x20000000>; > + }; Maybe add a comment that there's 1GB variants as well? > + > + vcck: regulator-vcck { > + compatible = "regulator-fixed"; > + regulator-name = "VCCK"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + vin-supply = <&dc_5v>; > + > + /* > + * This is controlled by GPIOAO_9 we reserve this but > + * claiming it as done bellow reset the board anyway s/bellow/below/ > +&spifc { > + status = "okay"; > + pinctrl-0 = <&nor_pins>; > + pinctrl-names = "default"; > + > + w25q32: spi-flash@0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <3000000>; Is this 3MHz a limitation of the flash, board layout or SPI controller? -- Bye, Peter Korsgaard