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From:   Robert Richter <rrichter@cavium.com>
To:     Marc Zyngier <marc.zyngier@arm.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>
CC:     Will Deacon <will.deacon@arm.com>,
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        John Garry <john.garry@huawei.com>,
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        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Richter, Robert" <Robert.Richter@cavium.com>
Subject: [PATCH 2/2] irqchip/gic-v3-its: Use CMA for allocation of large
 device tables
Thread-Topic: [PATCH 2/2] irqchip/gic-v3-its: Use CMA for allocation of large
 device tables
Thread-Index: AQHUfS1OydriUw4dmUeW0piSOGtXyA==
Date:   Thu, 15 Nov 2018 21:51:04 +0000
Message-ID: <20181115215012.23922-3-rrichter@cavium.com>
References: <20181115215012.23922-1-rrichter@cavium.com>
In-Reply-To: <20181115215012.23922-1-rrichter@cavium.com>
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The gicv3-its device table may have a size of up to 16MB. With 4k
pagesize the maximum size of memory allocation is 4MB. Use CMA for
allocation of large tables.

We use the device managed version of dma_alloc_coherent(). Thus, we
don't need to release it manually on device removal.

Signed-off-by: Robert Richter <rrichter@cavium.com>
---
 drivers/irqchip/irq-gic-v3-its.c | 113 ++++++++++++++++++++++++++++-------=
----
 1 file changed, 82 insertions(+), 31 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-=
its.c
index a4b1b2fcb60f..6ba221aa27b9 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -23,6 +23,7 @@
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/dma-iommu.h>
+#include <linux/dma-mapping.h>
 #include <linux/efi.h>
 #include <linux/interrupt.h>
 #include <linux/irqdomain.h>
@@ -1732,6 +1733,41 @@ static void its_write_baser(struct its_node *its, st=
ruct its_baser *baser,
 	baser->val =3D its_read_baser(its, baser);
 }
=20
+static void *its_alloc_table(struct its_node *its, u32 order,
+			u64 *baser_phys)
+{
+	dma_addr_t dma_handle;
+	void *base;
+
+	if (order < MAX_ORDER) {
+		base =3D (void *)devm_get_free_pages(&its->dev,
+						GFP_KERNEL | __GFP_ZERO,
+						order);
+		*baser_phys =3D virt_to_phys(base);
+		return base;
+	}
+
+	/* try using CMA */
+	base =3D dmam_alloc_coherent(&its->dev,
+				PAGE_ORDER_TO_SIZE(order),
+				&dma_handle,
+				GFP_KERNEL | __GFP_ZERO);
+	*baser_phys =3D base ? dma_handle : 0;
+	return base;
+}
+
+static void its_free_table(struct its_node *its, u32 order, void *base,
+			u64 baser_phys)
+{
+	if (order < MAX_ORDER) {
+		devm_get_free_pages(&its->dev, GFP_KERNEL | __GFP_ZERO, order);
+		return;
+	}
+
+	dmam_free_coherent(&its->dev, PAGE_ORDER_TO_SIZE(order), base,
+			(dma_addr_t)baser_phys);
+}
+
 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
 			   u64 cache, u64 shr, u32 psz, u32 order,
 			   bool indirect)
@@ -1753,12 +1789,20 @@ static int its_setup_baser(struct its_node *its, st=
ruct its_baser *baser,
 		order =3D get_order(GITS_BASER_PAGES_MAX * psz);
 	}
=20
-	base =3D (void *)devm_get_free_pages(&its->dev, GFP_KERNEL | __GFP_ZERO,
-					   order);
-	if (!base)
-		return -ENOMEM;
+	base =3D its_alloc_table(its, order, &baser_phys);
=20
-	baser_phys =3D virt_to_phys(base);
+	if (!base && order >=3D MAX_ORDER) {
+		order =3D MAX_ORDER - 1;
+		dev_warn(&its->dev, "%s Table too large, reduce ids %u->%u, no CMA memor=
y available\n",
+			its_base_type_string[type], its->device_ids,
+			ilog2(PAGE_ORDER_TO_SIZE(order) / (int)esz));
+		goto retry_alloc_baser;
+	}
+
+	if (!base) {
+		dev_err(&its->dev, "Failed to allocate device table\n");
+		return -ENOMEM;
+	}
=20
 	/* Check if the physical address of the memory is above 48bits */
 	if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
@@ -1816,29 +1860,27 @@ static int its_setup_baser(struct its_node *its, st=
ruct its_baser *baser,
 		goto retry_baser;
 	}
=20
-	if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
-		/*
-		 * Page size didn't stick. Let's try a smaller
-		 * size and retry. If we reach 4K, then
-		 * something is horribly wrong...
-		 */
-		devm_free_pages(&its->dev, (unsigned long)base);
-		baser->base =3D NULL;
-
-		switch (psz) {
-		case SZ_16K:
-			psz =3D SZ_4K;
-			goto retry_alloc_baser;
-		case SZ_64K:
-			psz =3D SZ_16K;
-			goto retry_alloc_baser;
+	if (val !=3D tmp) {
+		its_free_table(its, order, base, baser_phys);
+
+		if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
+			/*
+			 * Page size didn't stick. Let's try a smaller
+			 * size and retry. If we reach 4K, then
+			 * something is horribly wrong...
+			 */
+			switch (psz) {
+			case SZ_16K:
+				psz =3D SZ_4K;
+				goto retry_alloc_baser;
+			case SZ_64K:
+				psz =3D SZ_16K;
+				goto retry_alloc_baser;
+			}
 		}
-	}
=20
-	if (val !=3D tmp) {
 		dev_err(&its->dev, "%s doesn't stick: %llx %llx\n",
 		       its_base_type_string[type], val, tmp);
-		devm_free_pages(&its->dev, (unsigned long)base);
 		return -ENXIO;
 	}
=20
@@ -1862,7 +1904,6 @@ static bool its_parse_indirect_baser(struct its_node =
*its,
 				     u32 psz, u32 *order, u32 ids)
 {
 	u64 tmp =3D its_read_baser(its, baser);
-	u64 type =3D GITS_BASER_TYPE(tmp);
 	u64 esz =3D GITS_BASER_ENTRY_SIZE(tmp);
 	u64 val =3D GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
 	u32 new_order =3D *order;
@@ -1898,12 +1939,6 @@ static bool its_parse_indirect_baser(struct its_node=
 *its,
 	 * feature is not supported by hardware.
 	 */
 	new_order =3D max_t(u32, get_order(esz << ids), new_order);
-	if (new_order >=3D MAX_ORDER) {
-		new_order =3D MAX_ORDER - 1;
-		ids =3D ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
-		dev_warn(&its->dev, "%s Table too large, reduce ids %u->%u\n",
-			its_base_type_string[type], its->device_ids, ids);
-	}
=20
 	*order =3D new_order;
=20
@@ -3522,6 +3557,22 @@ static int __init its_init_one(struct its_node *its)
 		return err;
 	}
=20
+	/*
+	 * Setup dma_ops to be used with dmam_alloc_coherent() for its
+	 * device table allocation. Since the device table is
+	 * exclusively used by the device only we can mark this mem as
+	 * coherent.
+	 */
+	arch_setup_dma_ops(&its->dev, 0, 0, NULL, true);
+
+	err =3D dma_coerce_mask_and_coherent(&its->dev, DMA_BIT_MASK(64));
+	if (err)
+		err =3D dma_coerce_mask_and_coherent(&its->dev, DMA_BIT_MASK(32));
+	if (err) {
+		dev_warn(&its->dev, "Unable to set DMA mask\n");
+		goto fail;
+	}
+
 	its_base =3D devm_ioremap(&its->dev, its->phys_base, its->phys_size);
 	if (!its_base) {
 		dev_warn(&its->dev, "Unable to map ITS registers\n");
--=20
2.11.0