Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp432708imu; Fri, 16 Nov 2018 04:58:24 -0800 (PST) X-Google-Smtp-Source: AJdET5cuFzIsF4Rtitahw071tKQthxfxWmKTb3rHqnj1dShCRz0bENz/wx+wegni6ySmrC66+Yrb X-Received: by 2002:a63:5c41:: with SMTP id n1mr8484537pgm.1.1542373104066; Fri, 16 Nov 2018 04:58:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542373104; cv=none; d=google.com; s=arc-20160816; b=BLxJ+x9bVbBbjctotcDpFIMCCeRPZ/uNGkF78SOG6LEHfhvyNZMTpwNtLtxZz2C1F6 IWVdHGC21G9iOUqMRSNcz+bArYVMbbTLns9RImvYoASQ96hll1f6xQFAd8ACO+XD5cZg UraHhQiyinevpqodhgbTFHTFUfiYbYC09VbR7q+Z6NIUHRxuSKM9gzhXXKDaPKFxvGPa FY+0VkUoHQeMsG2uNQ7tUviCRcmZnrm8xOHnK9a0YBp1rSJrCpavnRjgSEOH07u3OUyi lZIlZYCpB9y3q/SiakIMB7rPGjEiM7vLMXIugL+c6uTlwKHLBtXg3duYNvKEK9+Uyrec Tg8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jmoX/+oNv6t1y+fxEI4pgINaYgFfqKMcHSb7tlu5+vY=; b=TBLT9DKosM06Awl3eUdSgr8A3MIhh64TMUTwhWKo7ckRSOqwBwt/aU6q9Dah3yUH0J DeXq6vb6MlAh0TtLRnGMZOAyMUDa3CxttEGu0ANjQS27w7G5CsX9VAVuN7WhAK9OkFC9 sfStRdQTznGuU1pyoG6QhrVrmP+2Mx2NxP6X7lkhA4poYANFQkLQMQVM+6QEA9Q8bXbh QSZV8ysVXLcDy2/nO1YwXmBIaM47U7eT680AgyEd3nHFy1AWAMHIYnPGiohy4BK6r+wR HzmceMcYij2DXMv/BGtwmthWicjv+Iq/c6XtpWxT47BPnV2oaIv1sRqcGHvntDjwd4Yy yyZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b="YAWY/21c"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y3-v6si30132918pfe.42.2018.11.16.04.58.10; Fri, 16 Nov 2018 04:58:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b="YAWY/21c"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389930AbeKPXIU (ORCPT + 99 others); Fri, 16 Nov 2018 18:08:20 -0500 Received: from mail.kernel.org ([198.145.29.99]:34082 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727965AbeKPXIU (ORCPT ); Fri, 16 Nov 2018 18:08:20 -0500 Received: from ziggy.de (unknown [93.176.133.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2ACCA22507; Fri, 16 Nov 2018 12:55:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1542372962; bh=WW16hmSAu3cDtCEXwV03kGOnejJmROkh16btrAr+l3k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YAWY/21co5Dyko1/K6UuFZ7erUSseMyADNqy9aUyRSe+lOnQm+H8hTvCbKrvwHJu6 3+CSvI9aRJufHYehXxc9/v5KxACxOVCm++0Z0fAlSkqAPuklh3fhUiFHGnkRonm01r cNPJuvKrERzSnYtd6ofCHSDnDFv5TStSpRn5+Jg8= From: matthias.bgg@kernel.org To: robh+dt@kernel.org, mark.rutland@arm.com, ck.hu@mediatek.com, p.zabel@pengutronix.de, airlied@linux.ie, mturquette@baylibre.com, sboyd@codeaurora.org, ulrich.hecht+renesas@gmail.com, laurent.pinchart@ideasonboard.com, matthias.bgg@gmail.com Cc: sean.wang@mediatek.com, sean.wang@kernel.org, rdunlap@infradead.org, wens@csie.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Matthias Brugger Subject: [PATCH v5 08/12] dt-bindings: mediatek: Change the binding for mmsys clocks Date: Fri, 16 Nov 2018 13:54:45 +0100 Message-Id: <20181116125449.23581-9-matthias.bgg@kernel.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181116125449.23581-1-matthias.bgg@kernel.org> References: <20181116125449.23581-1-matthias.bgg@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Matthias Brugger On SoCs with no publical available HW or no working graphic stack we change the devicetree binding for the mmsys clock part. This way we don't need to register a platform device explicitly in the drm driver. Instead we can create a mmsys child which invokes the clock driver. Signed-off-by: Matthias Brugger --- .../bindings/arm/mediatek/mediatek,mmsys.txt | 21 ++++++++++++------- .../display/mediatek/mediatek,disp.txt | 4 ++++ 2 files changed, 18 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt index 4468345f8b1a..d4e205981363 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt @@ -1,4 +1,4 @@ -Mediatek mmsys controller +Mediatek mmsys clock controller ============================ The Mediatek mmsys controller provides various clocks to the system. @@ -6,18 +6,25 @@ The Mediatek mmsys controller provides various clocks to the system. Required Properties: - compatible: Should be one of: - - "mediatek,mt2712-mmsys", "syscon" - - "mediatek,mt6797-mmsys", "syscon" + - "mediatek,mt2712-mmsys-clk", "syscon" + - "mediatek,mt6797-mmsys-clk", "syscon" - #clock-cells: Must be 1 -The mmsys controller uses the common clk binding from +The mmsys clock controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h. +It is a child of the mmsys block, see binding at: +Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt Example: -mmsys: clock-controller@14000000 { - compatible = "mediatek,mt8173-mmsys", "syscon"; +mmsys: syscon@14000000 { + compatible = "mediatek,mt2712-mmsys", "syscon", "simple-mfd"; reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; + + mmsys_clk: clock-controller@14000000 { + compatible = "mediatek,mt2712-mmsys-clk"; + #clock-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index 4b008d992398..38c708cb7e55 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -54,6 +54,10 @@ Required properties (all function blocks): DPI controller nodes have multiple clock inputs. These are documented in mediatek,dsi.txt and mediatek,dpi.txt, respectively. +Some chips have a separate binding for the clock controller, which is a child node +of the mmsys device, for more information see: +Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt + Required properties (DMA function blocks): - compatible: Should be one of "mediatek,-disp-ovl" -- 2.19.1