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[209.132.180.67]) by mx.google.com with ESMTP id 11si32723946pgy.408.2018.11.17.04.20.31; Sat, 17 Nov 2018 04:20:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G6sCiHeW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726246AbeKQWfI (ORCPT + 99 others); Sat, 17 Nov 2018 17:35:08 -0500 Received: from mail-lf1-f68.google.com ([209.85.167.68]:44817 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725980AbeKQWfH (ORCPT ); Sat, 17 Nov 2018 17:35:07 -0500 Received: by mail-lf1-f68.google.com with SMTP id z13so18266509lfe.11 for ; Sat, 17 Nov 2018 04:18:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=CwcZgS6Si8t6pVK8iLN8oUsF9P5jKc1FkAFCju2jRJg=; b=G6sCiHeWI0jperDcoeGMpNnvCQK5Vpj5BiA9QM+LbgCxL2NezLMkVWFMB/TDS5c6N5 GwbtWfMBi+4g4p4F45l7HMmR1qz78QOQvzSZ6ujBb2pyXEl/F04j0OcLl/rVIwPGT7WJ vGiQN6Vgvjnjvjgtk8Nl/9fvMsSuCSto6u81c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=CwcZgS6Si8t6pVK8iLN8oUsF9P5jKc1FkAFCju2jRJg=; b=ZJ9vHGe0JnIf3ZCmom2rlpyozEYSaRAv6zQyTg50JHj1kKNHzQcy4wlPoiC1mjldAQ HVKjZXc9NNLQCyUhUbiFTsABA/B2wCaObdbZFI138cykzmoLgL6J4+eqz4p74MAYHfG2 H6OAn5qQbYNyzYPU0fn8RC9XiAVV0vY8Hq14nbPb0aXkcJ8a2GQgbhUlGpGsfA9gkA+n jHADgCnRoCgBBE9cPrHNHkJNnfHsw4jgOSPasuZf6T15icSUo9pVanEQpzCX83EOvhlS fg3hYrelXC4UUfF7CbuBUWjlJSo4E4ScLfdAD8EpB0ZzbTVzfMVMFWb4g/bergh3SvaE zh5w== X-Gm-Message-State: AGRZ1gKQbbIF3nhe+c34wwJnMYd/wR3ZnK9cus2ZeRPFXHuZJClDvkhw rwU0iF97DYcSwkRIG+WfSHE9TP8iOS+7ZVF2uwdYKQ== X-Received: by 2002:a19:5154:: with SMTP id f81mr7757418lfb.96.1542457115612; Sat, 17 Nov 2018 04:18:35 -0800 (PST) MIME-Version: 1.0 References: <20181111210047.30375-1-heiko@sntech.de> In-Reply-To: <20181111210047.30375-1-heiko@sntech.de> From: Linus Walleij Date: Sat, 17 Nov 2018 13:18:23 +0100 Message-ID: Subject: Re: [PATCH 1/2] pinctrl: rockchip: allow specifying the regmap location for pin-routes To: =?UTF-8?Q?Heiko_St=C3=BCbner?= Cc: "open list:GPIO SUBSYSTEM" , Linux ARM , "open list:ARM/Rockchip SoC..." , "linux-kernel@vger.kernel.org" , Shawn Lin , David Wu , heiko.stuebner@bq.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Nov 11, 2018 at 10:01 PM Heiko Stuebner wrote: > From: Heiko Stuebner > > Right now we expect the pin-rounting settings to be in the same area > as the iomux setting itself. And while that seems to be true for all > newer Rockchip socs, back in the wild west days of old this wasn't true. > > Nowadays pin settings in the GRF normally stay in the GRF and the same > is true for pins configured from PMU registers. But old socs like the > rk3188 really sprinkle pin settings somewhat randomly through both > for its bank0. > > Therefore add the option to specify a location for the route setting, > so that we can map older socs correctly. We'll keep "same" as the > default, so that we only need to specify a location in the corner-cases > described above. > > Signed-off-by: Heiko Stuebner Patch applied with David's review tag. Yours, Linus Walleij