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[209.132.180.67]) by mx.google.com with ESMTP id b8si33682465pgi.575.2018.11.17.07.14.51; Sat, 17 Nov 2018 07:15:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=vnn8UZw5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726450AbeKRBas (ORCPT + 99 others); Sat, 17 Nov 2018 20:30:48 -0500 Received: from mail.kernel.org ([198.145.29.99]:39686 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726065AbeKRBas (ORCPT ); Sat, 17 Nov 2018 20:30:48 -0500 Received: from mail-qk1-f182.google.com (mail-qk1-f182.google.com [209.85.222.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2827420825; Sat, 17 Nov 2018 15:13:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1542467630; bh=LEHXWTTLmnYfMHUGwfsNdp/AMHvF3vpS6ufqMzrgrlY=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=vnn8UZw52dtanEcpqsaoCxdJRQd0g4ixwMpbBLZAP2SJVOXc4Ty3ThugmB3G0pv8c 0ek5wk9cQ6vtrtRQ7Ab0GerduELmhU89CVLEoFOSTzCU8Ghw5rc67Mz3U047J0v9/a zpCJ8fxwKgm/Fp23hsFrwUx0WAv+sxZDOE09MZkM= Received: by mail-qk1-f182.google.com with SMTP id w204so42228863qka.2; Sat, 17 Nov 2018 07:13:50 -0800 (PST) X-Gm-Message-State: AGRZ1gI5V6FQGzg7XaeE0M+mziyKXAOWhXV4I0Fjd/G17Z7/U3c9RQg0 KKTPoMBuc+zcNb/7rp7q3AXLAu1ghdL6Af5TPw== X-Received: by 2002:a37:5686:: with SMTP id k128mr13423617qkb.29.1542467629293; Sat, 17 Nov 2018 07:13:49 -0800 (PST) MIME-Version: 1.0 References: <20181108070449.23572-1-shawn.guo@linaro.org> <20181108070449.23572-2-shawn.guo@linaro.org> <5bea0ed8.1c69fb81.8715.38b2@mx.google.com> <20181113034200.GD20049@tiger> In-Reply-To: <20181113034200.GD20049@tiger> From: Rob Herring Date: Sat, 17 Nov 2018 09:13:38 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 1/2] dt-bindings: phy: Add Qualcomm Synopsys High-Speed USB PHY binding To: Shawn Guo Cc: Kishon Vijay Abraham I , Sriharsha Allenki , Anu Ramanathan , Bjorn Andersson , Vinod , linux-arm-msm , devicetree@vger.kernel.org, "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 12, 2018 at 9:42 PM Shawn Guo wrote: > > Hi Rob, > > On Mon, Nov 12, 2018 at 01:24:51PM -0600, Rob Herring wrote: > > On Thu, Nov 08, 2018 at 03:04:48PM +0800, Shawn Guo wrote: > > > From: Sriharsha Allenki > > > > > > It adds bindings for Synopsys 28nm femto phy controller that supports > > > LS/FS/HS usb connectivity on Qualcomm chipsets. > > > > > > Signed-off-by: Sriharsha Allenki > > > Signed-off-by: Anu Ramanathan > > > Signed-off-by: Bjorn Andersson > > > Signed-off-by: Shawn Guo > > > --- > > > .../phy/qcom,snps-28nm-usb-hs-phy.txt | 101 ++++++++++++++++++ > > > 1 file changed, 101 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt > > > > > > diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt b/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt > > > new file mode 100644 > > > index 000000000000..75e7a09dd558 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt > > > @@ -0,0 +1,101 @@ > > > +Qualcomm Synopsys 28nm Femto phy controller > > > +=========================================== > > > + > > > +Synopsys 28nm femto phy controller supports LS/FS/HS usb connectivity on > > > +Qualcomm chipsets. > > > + > > > +Required properties: > > > + > > > +- compatible: > > > + Value type: > > > + Definition: Should contain "qcom,usb-snps-hsphy". > > > > SoC specific compatible? > > Agreed. A SoC prefixed compatible would be more specific and scalable > for handling different programming model of the same IP. I will use > "qcom,qcs404-usb-hsphy" in v3. > > > > > > + > > > +- reg: > > > + Value type: > > > + Definition: USB PHY base address and length of the register map. > > > + > > > +- #phy-cells: > > > + Value type: > > > + Definition: Should be 0. > > > + > > > +- clocks: > > > + Value type: > > > + Definition: See clock-bindings.txt section "consumers". List of > > > + three clock specifiers for reference, phy core and > > > + sleep clocks. > > > + > > > +- clock-names: > > > + Value type: > > > + Definition: Names of the clocks in 1-1 correspondence with the "clocks" > > > + property. Must contain "ref", "phy" and "sleep". > > > + > > > +- resets: > > > + Value type: > > > + Definition: See reset.txt section "consumers". PHY reset specifiers > > > + for phy core and POR resets. > > > + > > > +- reset-names: > > > + Value type: > > > + Definition: Names of the resets in 1-1 correspondence with the "resets" > > > + property. Must contain "phy" and "por". > > > + > > > +- vdd-supply: > > > + Value type: > > > + Definition: phandle to the regulator VDD supply node. > > > + > > > +- vdda1p8-supply: > > > + Value type: > > > + Definition: phandle to the regulator 1.8V supply node. > > > + > > > +- vdda3p3-supply: > > > + Value type: > > > + Definition: phandle to the regulator 3.3V supply node. > > > + > > > +- qcom,vdd-voltage-level: > > > + Value type: > > > + Definition: This is a list of three integer values where > > > + each value corresponding to voltage corner in uV. > > > + > > > +Optional properties: > > > + > > > +- extcon: > > > + Value type: > > > + Definition: Should contain the vbus extcon. > > > > Don't use extcon for new bindings. Use usb-connector binding. > > Okay, I just did a bit of research and found that 'extcon' is becoming > a deprecated DT property recently and we should OF graph bindings to > specify the connector. Will do in v3. > > > > > > + > > > +- qcom,init-seq: > > > + Value type: > > > + Definition: Should contain a sequence of tuples to > > > + program 'value' into phy register at 'offset' with 'delay' > > > + in us afterwards. > > > > If we wanted this type of thing in DT, we'd have a generic binding (or > > forth). > > Right now, this is a qualcomm usb phy specific bindings - first used in > qcom,usb-hs-phy.txt and I extended it a bit for my phy. As this is not > a so good hardware description, I'm a little hesitated to make it > generic for other platforms to use in general. What about we put off it > a little bit until we see more platforms need the same thing? I'm not saying I want it generic. Quite the opposite. I don't think we should have it either generically or vendor specific. The main thing I have a problem with is the timing information because then we're more that just data. Without that we're talking about a bunch of properties for register fields or just raw register values in DT. That becomes more of a judgement call. There's not too much value in making a driver translate a bunch of properties just to stuff them into registers on init. But then just allowing any raw register value to be in DT could be easily abused. Rob